Course Description

Whether you’re new to RISC-V or a seasoned expert looking to integrate RISC-V into your FPGA solution, this course is tailored for you. It covers comprehensive RISC-V specifications, including the user-level instruction set architecture (ISA), privileged architecture, Control and Status Registers (CSRs) and more. You will explore the RISC-V models supported on Lattice IP Cores and how their features align with the RISC-V specifications. The course culminates with a demonstration of implementing RISC-V on Lattice hardware, providing hands-on reinforcement of the concepts learned.

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