614 results found for ""
Reset Strategy & Best Practices
Advanced
·
1hr 39mins
Free
This training aims to provide participants with a comprehensive understanding of different types of reset implementations, their impact on design reliability, and the best practices to avoid hardware related problems.
MIPI – Ethernet – HDMI Reference Design
Advanced
·
1hr 05mins
Free
Get an overview of the MIPI - Ethernet - HDMI Reference Design which also covers the features, architecture, design considerations, clockings, and deep-dive into various subsystems included in the reference design.
Using MachXO5TM-NX Root-of-Trust (RoT) Device
Advanced
·
1hr 34mins
Free
This presentation covers the overall high-level flow of using MachXO5-NX Root of Trust device which includes image creation, provisioning flow, configuration/flow, user mode application, and user design update flow.
Lattice FPGA SW Tools 2024.2 Updates
Basic
·
1hr 03mins
Free
This session shares the latest tool updates, fixed issues, and known issues of Lattice's Radiant and Propel 2024.2 release.
Avant: Development Boards – Overview
Basic
·
1mins
Free
This module introduces Lattice Avant development boards that are available in the market.
FPGA Reset: Concepts, Applications, and Types
Basic
·
39mins
Free
Explore the fundamental principles of FPGA resets, understand their real-world applications, and gain insights into different types of resets. Discover how effective reset strategies can enhance system stability and performance in various scenarios, ensuring your systems run smoothly and efficiently.
FPGA Reset: Introductions to Reset Concepts, Applications, and Types
Basic
·
9mins
Free
This module covers fundamental reset concepts, discussing why resets are needed, types of resets, and their impact on system stability and reliability.
FPGA Reset: Reset Role in Timing Closure
Basic
·
6mins
Free
Examine the role of reset signals on timing closure, addressing timing parameters and metastability issues that arise from improper reset handling.​
FPGA Reset: Asynchronous Reset
Basic
·
12mins
Free
This module discusses asynchronous resets, focusing on its implementation, potential challenges like timing violations, and techniques to minimize metastability risks.
FPGA Reset: Hybrid Reset
Basic
·
3mins
Free
Introduces the hybrid reset approach, combining asynchronous assertion with synchronous de-assertion to enhance reliability and reduce timing issues.​