RISC-V: Specification – Priviledged Architecture, Control and Status Registers (CSRs)

Module Description

Interested in gaining insights on RISC-V privileged architectures and privilege levels such as user mode, supervisor mode, and machine mode? This module will be helpful. An overview of Control and Status Registers (CSRs), including machine trap setup CSRs like mstatus, will also be covered as we walk you through RISC-V privileged architectures and privilege levels.