274 results found for ""
Lattice Avant Platform Overview
Basic
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15mins
Free
Unveiling Lattice Avant, a new FPGA platform purpose-built to bring the Lattice’s power efficient architecture, small size, and performance leadership to mid-range FPGAs. Explore Avant's features, that offer best-in-class power efficiency, advanced connectivity, and optimized compute, all in a small footprint. Find out how the design choices for Avant architecture resulted in power and performance optimizations. Learn about the Avant-E family and portfolio of development tools to get you started on developing with Avant.
Avant: Advantages
Basic
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3mins
Free
Find out how Avant's modernized features are setting it apart from other FPGAs in its class. See how Avant is leading with lower power, smaller footprint, and better performance.
Certus-NX / CertusPro-NX: Architecture – Cryptographic Engine (CRE), Trace ID
Intermediate
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04mins
1 Credit
Learn about the cryptographic engine (CRO), and other options that can enhance your FPGA usage, such as TraceID and pin migration. The features covered here apply to the Lattice CrossLink-NX, Certus-NX and CertusPro-NX devices.
Avant: Features – Low Power Architecture
Basic
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9mins
Free
Discover the design choices for Avant architecture that resulted in power and performance optimizations, including the advantages of going with LUT4 (vs. LUT6) and improved routability.
Certus-NX / CertusPro-NX: Architecture – Configuration, JTAG Boundary Scan, SEU Handling
Intermediate
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6mins
1 Credit
Learn about the various configuration related features, including JTAG boundary scan testability, features & support during device configuration, and Single-Event Upset (SEU) handling. The features covered here apply to the Lattice CrossLink-NX, Certus-NX and CertusPro-NX devices.
Certus-NX / CertusPro-NX: Architecture – SerDes/PCS Protocols, Modes, Reference Clock
Intermediate
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4mins
1 Credit
In this module, we summarize all the protocols and modes supported by Lattice CertusPro-NX's SerDes/PCS. We also explain the data/signal flow during the operation of each mode, and the Reference Clock architecture.
Certus-NX / CertusPro-NX: Architecture – SerDes/PCS Multi-protocol PCS (MPCS) Part 2
Intermediate
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09mins
1 Credit
Continue to learn about the SerDes/PCS architecture and the blocks that allow it to support various communications protocols. In this module, we cover the 64B/66B PCS block in the multi-protocol PCS (MPCS) block and the PMA-only mode. The blocks covered here are specific to Lattice CertusPro-NX.
Certus-NX / CertusPro-NX: Architecture – SerDes/PCS Multi-protocol PCS (MPCS) Part 1
Intermediate
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10mins
1 Credit
Continue to learn about the SerDes/PCS architecture and the blocks that allow it to support various communications protocols. In this module, we cover the multi-protocol PCS (MPCS) and functional blocks such as the 8B/10B PCS block. The blocks covered here are specific to Lattice CertusPro-NX.
Certus-NX / CertusPro-NX: Architecture – PCIe Hard IP
Intermediate
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04mins
1 Credit
Learn about the PCIe Hard IP (Gen 2 and Gen 3) and its supported modes. The PCIe Gen2 block covered here applies to the Lattice Certus-NX devices, while the PCIe Gen3 block applies to the CertusPro-NX devices.
Certus-NX / CertusPro-NX: Architecture – Analog to Digital Convertor (ADC)
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05mins
1 Credit
Take a look at the architecture and functions available on the Analog to Digital Convertor (ADC). The blocks covered here apply to the Lattice CrossLink-NX, Certus-NX and CertusPro-NX devices.
Certus-NX / CertusPro-NX: Architecture – sysI/O Buffer, I2C Hard IP
Intermediate
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08mins
1 Credit
Learn about the architecture and functions supported by the sysI/O Buffer and I2C Hard IP. The blocks covered here apply to the Lattice CrossLink-NX, Certus-NX and CertusPro-NX devices.