38 results found for ""
Converting From Xilinx to Lattice: Architecture Differences
Intermediate
·
1mins
3 Credit
Discover the device architecture differences between Xilinx and Lattice to make a fair comparison. Gain insights on conversion steps to save time during design migration.
Reveal Analyzer and Controller
Intermediate
·
1hr 13mins
Free
Gain valuable insights into effective FPGA hardware debugging with our comprehensive course. Discover the power of Reveal Analyzer and Controller, interactive tools that enable you to observe and analyze debug cores in your Lattice FPGA projects. Navigate your debugging process with confidence and optimize the performance of your FPGA designs.
RISC-V Solutions with Lattice
Advanced
·
1hr 32mins
2 Credit
Whether you're new to RISC-V or a seasoned expert looking to integrate RISC-V into your FPGA solution, this course is tailored for you. It covers comprehensive RISC-V specifications, including the user-level instruction set architecture (ISA), privileged architecture, Control and Status Registers (CSRs) and more. You will explore the RISC-V models supported on Lattice IP Cores and how their features align with the RISC-V specifications. The course culminates with a demonstration of implementing RISC-V on Lattice hardware, providing hands-on reinforcement of the concepts learned.
RISC-V: Lattice RISC-V Cores
Advanced
·
13mins
2 Credit
This module provides a comprehensive overview of the Lattice RISC-V offerings, including detailed insights into the corresponding devices that support these features. You will also gain in-depth understanding of how the Lattice RISC-V cache works, including its partitioning and how a CPU designer can effectively map a large number of main memory blocks into a smaller number of cache lines.
RISC-V: Physical Memory Protection, Page-based Virtual Memory
Advanced
·
07mins
2 Credit
In addition to covering the supported aspects of Lattice RISC-V, this module also provides a brief explanation of other key topics, such as the physical memory protection unit and page-based virtual memory, as well as the operating systems, PLIC, and CLINT interrupt controllers.
RISC-V: Specification – Machine Trap Setup CSRs
Advanced
·
9mins
2 Credit
This continuation module provides a comprehensive overview of the remaining machine trap setup Control and Status Registers (CSRs), including misa, mtvec, and more, giving you a complete understanding of these critical registers and their roles in the RISC-V machine trap setup.
RISC-V: Specification – Priviledged Architecture, Control and Status Registers (CSRs)
Advanced
·
11mins
2 Credit
Interested in gaining insights on RISC-V privileged architectures and privilege levels such as user mode, supervisor mode, and machine mode? This module will be helpful. An overview of Control and Status Registers (CSRs), including machine trap setup CSRs like mstatus, will also be covered as we walk you through RISC-V privileged architectures and privilege levels.
RISC-V: Specification – Register File
Advanced
·
12mins
2 Credit
Ready to level up your understanding of RISC-V register files? This module dives into the intricacies of 32-bit RISC-V register file conventions, instruction formats, opcode operations, address handling, and handling of interrupts, exceptions, and traps.
RISC-V: Specification – Instruction Set
Advanced
·
12mins
2 Credit
This module provides a detailed overview of the RISC-V specifications, focusing on the user-level Instruction Set Architecture (ISA) or unprivileged ISA. You will be introduced to the instruction set variant supported at Lattice, as well as the naming conventions and extensions used in RISC-V.
Ethernet: Evaluation Board
Advanced
·
05mins
2 Credit
Explore the range of evaluation boards specifically designed for high-speed link testing and communication, as well as applications such as sensAI development or uncompressed video. Discover how these evaluation boards can serve as valuable tools for your design process, and get insights from a demo on a reference design to further guide your Ethernet implementation.
Ethernet: Implementation – Jitter, PPM, Status and Configuration Registers
Advanced
·
13mins
2 Credit
Discover the importance of clock quality for 10 Gb Ethernet compliance and SerDes Tx/Rx operation in this module. Learn about clock quality measurement techniques and gain insights on accessing MPCS status and configuration registers using APB or MDIO interfaces.
Ethernet: Implementation – Debug Signals, Loopback Modes
Advanced
·
10mins
2 Credit
Understand how to effectively debug and monitor the operation of the 10 Gb Ethernet PCS IP core by learning about key debugging signals and loopback modes. Gain valuable insights into ensuring proper operation and troubleshooting any issues that may arise during implementation.