Security Updates
Advanced . 1hr 11mins
In this presentation, a demo for Server Architecture for Security in the form of DC-SCM with/without PFR will be presented. Next, a detailed implementation flow for SupplyGuard will be presented and demoed.
Power Calculator Usage
Advanced . 48mins
This presentation covers the fundamentals of power consumption, then goes into the Power Calculator tool and usage. This includes the various modes, techniques to optimize power, and a hands-on session on utilizing the Power Calculator.
Avant – DDR5 & LPDDR4
Advanced . 26mins
This presentation provides an overview of LPDDR4/DDR4/DDR5 differences, then goes over a hands-on training on the full development process for implementing a LPDDR4 design on CP-NX.  The hands-on portion covers IP parameters, constraints, simulation, and debug.
PCIe Updates
Advanced . 46mins
This presentation provides an introduction to PCIe, a comparison of features supported on Avant vs. Nexus, and learnings from current PCIe issues.  It incorporates a demo of debugging a link-up issue, and includes a hands-on session to build a testbench from scratch.
Radiant & Propel Tools
Advanced . 2hrs 03mins
This presentation covers all updates for Radiant and Propel 2022.1, including updates from the Avant SW bash, known issues and major issues resolved.  It incorporates hands-on training and demo for selected new features such as Block Based Design, timing report updated, Reveal Controller’s User Register Function and Simulation Models, Propel’s modular design simplification and AXI IP creation.  The advanced SDC and timing closure best practices will also be covered.
Embedded System Design using Propel
Advanced . 1hr 39mins
This presentation covers the embedded system design flow, a Linker Script walk-through, and a guide to FreeRTOS. For each topic, hands-on training will be incorporated, including creating an embedded system using Propel, developing a linker, and running FreeRTOS.  
RISC-V Solutions with Lattice
Advanced . 1hr 32mins
2 Credit
Whether you're new to RISC-V or a seasoned expert looking to integrate RISC-V into your FPGA solution, this course is tailored for you. It covers comprehensive RISC-V specifications, including the user-level instruction set architecture (ISA), privileged architecture, Control and Status Registers (CSRs) and more. You will explore the RISC-V models supported on Lattice IP Cores and how their features align with the RISC-V specifications. The course culminates with a demonstration of implementing RISC-V on Lattice hardware, providing hands-on reinforcement of the concepts learned.
RISC-V: Lattice RISC-V Cores
Advanced . 13mins
2 Credit
This module provides a comprehensive overview of the Lattice RISC-V offerings, including detailed insights into the corresponding devices that support these features. You will also gain in-depth understanding of how the Lattice RISC-V cache works, including its partitioning and how a CPU designer can effectively map a large number of main memory blocks into a smaller number of cache lines.
RISC-V: Physical Memory Protection, Page-based Virtual Memory
Advanced . 07mins
2 Credit
In addition to covering the supported aspects of Lattice RISC-V, this module also provides a brief explanation of other key topics, such as the physical memory protection unit and page-based virtual memory, as well as the operating systems, PLIC, and CLINT interrupt controllers.
RISC-V: Specification – Machine Trap Setup CSRs
Advanced . 9mins
2 Credit
This continuation module provides a comprehensive overview of the remaining machine trap setup Control and Status Registers (CSRs), including misa, mtvec, and more, giving you a complete understanding of these critical registers and their roles in the RISC-V machine trap setup.
RISC-V: Specification – Priviledged Architecture, Control and Status Registers (CSRs)
Advanced . 11mins
2 Credit
Interested in gaining insights on RISC-V privileged architectures and privilege levels such as user mode, supervisor mode, and machine mode? This module will be helpful. An overview of Control and Status Registers (CSRs), including machine trap setup CSRs like mstatus, will also be covered as we walk you through RISC-V privileged architectures and privilege levels.
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