Module Description
This module provides a comprehensive overview of the Lattice RISC-V offerings, including detailed insights into the corresponding devices that support these features. You will also gain in-depth understanding of how the Lattice RISC-V cache works, including its partitioning and how a CPU designer can effectively map a large number of main memory blocks into a smaller number of cache lines.
If you wish to access this module, please purchase the course here.
Back to Course