Lattice Professional

Introducing the advanced security features for configuration that are available on all Lattice Nexus-based FPGAs. Learn how to implement these features through Lattice Radiant design software, including using the Programmer tool, and understanding the options available. Get insights into the lock policies and port locking mechanism to ensure proper usage of these security features.

Gain valuable insights into effective FPGA hardware debugging with our comprehensive course. Discover the power of Reveal Analyzer and Controller, interactive tools that enable you to observe and analyze debug cores in your Lattice FPGA projects. Navigate your debugging process with confidence and optimize the performance of your FPGA designs.

Dive into SerDes architecture with this course. We will take you through the basics of serializer-deserializer (SerDes) technology and explore the SerDes architecture on the new Avant platform. Gain a system-level overview of SerDes, followed by deeper dives into the blocks within the transmitter (TX) and receiver (RX). Learn about features critical to high-speed data transmission in the Physical Medium Attachment (PMA) and Physical Coding Sublayer (PCS) blocks, including the feed forward equalizer (FFE), decision feedback equalizer (DFE), and forward error correction (FEC).

See the origins of the Open Radio Access Network (ORAN), understand the key requirements for ORAN deployment, and discover Lattice’s ORAN Solution Stack 1.0, which provides all the resources you need to implement control data security.

The Sentry Solution Stack is a complete toolkit that includes everything needed to create a custom Platform Firmware Resiliency (PFR) implementation. In this course, learn fundamentals on how to establish a Platform Root of Trust (PRoT). Then, explore the IPs and FPGA features that you can use as building blocks for your RoT design.

In this course, you will learn all about the essential architecture components and building blocks of the CertusPro-NX physical coding sublayer (PCS) configured in 10GBASE-R Ethernet PHY. Discover how to implement 10 Gigabit Ethernet using Lattice devices, including practical design-related features, clocking, and tools. This course includes a demo using CertusPro-NX that takes you through each step of the implementation, from IP configuration to design constraints and simulation.

Interested in implementing PCIe using Lattice FPGAs? This course covers the fundamentals of the PCIe protocol, including understanding the PCIe protocol stack, how packet construction, link training, and enumeration is performed, and interrupt & error handling. Find out how you can configure the Lattice IPs to build a PCIe solution and get debug tips for resolving common issues.

Get an introduction to the external memory interfaces supported on the CertusPro-NX FPGA. This course starts with an overview of the DDR/LPDDR features and specifications. Then we cover how you can implement the DDR/LPDDR memory interface in your design, using all the architecture blocks, the Memory Controller Subsystem, and by ensuring proper initialization and training.

Explore how to create a Platform Firmware Resiliency (PFR) implementation with the Lattice Sentry Solution Stack. In this course, we will introduce the Best-Known Configurations (BKC) that can be used as your PFR architecture. Then, walk you through the key design implementation steps, beginning with using the Sentry Root of Trust (RoT) template design on Lattice Propel, through debugging the design with the Serial Debug Monitor. This course will also demonstrate the Sentry Demo Board and its various features.