Developing with CertusPro-NX

Explore the Lattice CertusPro-NX device architecture. In this course, we step through each and every architecture block, including the PLU, EBR-LRAM, DSP, clock network, IO, and various hard IPs (MIPI D-PHY, PCIe). For each block, learn about the features available and the architecture details to help you optimize your design.

Learn fundamentals of FPGA configuration and programming in this training course. Here, we focus on the features available on the Nexus FPGAs. Get an in-depth understanding of the configuration flow, explore the status and control registers for configuration status monitoring, and review best practices for configuration debug.

Get an introduction to the external memory interfaces supported on the CertusPro-NX FPGA. This course starts with an overview of the DDR/LPDDR features and specifications. Then we cover how you can implement the DDR/LPDDR memory interface in your design, using all the architecture blocks, the Memory Controller Subsystem, and by ensuring proper initialization and training.

Interested in implementing PCIe using Lattice FPGAs? This course covers the fundamentals of the PCIe protocol, including understanding the PCIe protocol stack, how packet construction, link training, and enumeration is performed, and interrupt & error handling. Find out how you can configure the Lattice IPs to build a PCIe solution and get debug tips for resolving common issues.

Introducing the CertusPro-NX Evaluation Board. Learn about flexible features that can help you with rapid prototyping and testing of your design, or for you to evaluate the features of the CertusPro-NX 100K LC FPGA.

Introducing the Hardware Checklist, which provides critical hardware implementation recommendations to assist in your FPGA board design. Learn about various considerations as you design a board for your FPGA, such as power design, configuration considerations, and handling sensitive pins.

Note: In this course, we use CertusPro-NX as an example of the FPGA we are designing for. However, the board design and development guidelines apply conceptually to any FPGA board you are developing.