Design Conversion: Converting From Intel to Lattice
Intermediate · 2hrs 46mins
3 Credit
In this course, you will learn about the essential differences in FPGA architecture between two companies. Additionally, you will explore the unique low power features offered by Lattice. The course will equip you with the techniques to convert your designs based on various design flow aspects, including selecting an equivalent device, understanding HDL compatibility, comparing tools, converting constraints files, and identifying available modes for device programming. GENERAL NOTICE: Other entity and product names used in this publication are for identification purposes only and may be trademarks of their respective holders.
Design Conversion: Converting From Xilinx to Lattice
Intermediate · 2hrs 48mins
3 Credit
Learn about the key FPGA architecture differences between the two companies, and explore the unique low power features offered by Lattice. This course will provide you the techniques to convert your designs based on the design flow aspects, which includes selecting an equivalent device, understanding the HDL compatibility, tools comparison, constraints files conversion, and available modes for device programming. GENERAL NOTICE: Other entity and product names used in this publication are for identification purposes only and may be trademarks of their respective holders.
Radiant: Design Flow
Basic · 15mins
Free
Learn about the Radiant development flow, including each process step and tools available.
Developing with ORAN Solution Stack
Intermediate · 1hr 15mins
1 Credit
Lattice ORAN Solution Stack covers the timing and synchronization requirements needed in various 3GPP/ORAN split deployment topologies. Discover how this solution stack provides secure and flexible synchronization based on the IEEE 1588v2 Precision Time Protocol (PTP) and various International Telecommunication Union (ITU) profiles. Multiple timing sources (DPLL/OCXO, and GNSS), PCIe Gen 2/3, and 10G Ethernet are supported. This course goes over wide aspects of the ORAN solution stack including how to configure and setup for the IEEE 1588 PTP and various ITU-T profiles, achieving time, frequency, and phase synchronization.
Power Calculator & Power Optimization Techniques
Intermediate · 1hr 20mins
1 Credit
Unlock Lattice's Low-Power FPGA Advantage: As FPGA densities and integration levels continue to rise, optimizing your designs for power efficiency is crucial. This course offers an in-depth exploration of FPGA power consumption mechanics, power estimation tools, optimization techniques, and head-to-head power calculations against the competition. Join us and unlock the secrets of FPGA power optimization!
Power Calculator: Lattice Power Advantage
Intermediate · 9mins
1 Credit
Uncover the Power Advantage: Delve into the unique strategic positioning of Lattice and how it contributes to superior power efficiency compared to the competition. Explore key aspects, including technology node, architecture, and fabric features, in this module.
Power Calculator: Modes of Power Calculation
Intermediate · 9mins
1 Credit
Discover the key modes of operation in the Power Calculator tool and their input files in the software process flow. Gain insights on the accurate calculation of power in this module.
Power Calculator: Power Basics in FPGA
Intermediate · 10mins
1 Credit
Enhance your understanding of power components and power basics in FPGA. Learn how to accurately calculate power dissipation and effectively set parameters in the thermal profile using our powerful Power Calculator Tool.
SerDes: Architecture – Physical Coding Sublayer (PCS)
Intermediate · 11mins
1 Credit
Gain an understanding of how PCS processes data into a format that meets PMA requirements. In this course, we will examine the TX and RX PCS in detail, covering TX blocks such as the block encoder, and forward error correction (FEC) block that improves the bit error rate (BER). Additionally, we will explore RX PCS blocks, which include the word aligner and elastic buffer. We end with a preview of the latest SerDes industry trends.
SerDes: Architecture – Physical Medium Attachment (PMA)
Intermediate · 13mins
1 Credit
This module provides a deep dive into the Avant TX and RX Physical Medium Attachment (PMA) architecture. You will examine TX blocks, including the feed forward equalizer (FFE), and RX blocks such as the continuous time linear equalizer (CTLE), variable gain amplifier (VGA), and decision feedback equalizer (DFE).
SerDes Architecture
Intermediate · 43mins
1 Credit
Dive into SerDes architecture with this course. We will take you through the basics of serializer-deserializer (SerDes) technology and explore the SerDes architecture on the new Avant platform. Gain a system-level overview of SerDes, followed by deeper dives into the blocks within the transmitter (TX) and receiver (RX). Learn about features critical to high-speed data transmission in the Physical Medium Attachment (PMA) and Physical Coding Sublayer (PCS) blocks, including the feed forward equalizer (FFE), decision feedback equalizer (DFE), and forward error correction (FEC).
Developing with sensAI Solution Stack: Utilizing sensAI Studio
Intermediate · 1hr 24mins
1 Credit
Welcome to Lattice's SensAI Studio course, where we invite you to accelerate your AI/ML application development on Lattice FPGAs. Learn about sensAI Studio’s easy-to-navigate user interface, jump start your development with the library of AI models that can be configured and trained for popular use cases, then easily port them to your targeted Lattice device. Using the Machine Learning Operations (MLOps) framework, you will learn about the innovative tools available on sensAI Studio that can help with building datasets, training your AI models, and managing collaborations within your team.
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