Developer Series

New to developing solutions using FPGAs (Field Programmable Gate Arrays)? This is the perfect place to start. In this course, we will provide fundamentals of digital logic and digital system design, and tie it to advantages of an FPGA-based implementation.

Ready to start implementing your design on a Lattice FPGA? This course will go over practical basics on how to start configuring the FPGA. Learn about all the various I/O settings. Understand timing characteristics and learn how to define proper timing specification. Explore the FPGA architecture and how it can be configured. Complete the picture by learning how to program the FPGA.

Get introduced to different techniques when developing the design that will be implemented in your FPGA. This course covers fundamental concepts, things to watch out for, and provides ideas to optimize your design for speed, area, power, or reliability. Learn about Clock Domain Crossing (CDC) – which is an important consideration when implementing a design in the FPGA – and solutions that can be used to overcome CDC issues. Be guided with best practices to help you design a more stable and optimized FPGA implementation.

This course focuses on Verilog, highlighting its importance in modeling digital integrated circuits and the RTL development process. Covering essential topics such as data values, assignments, statements, parameters, hardware circuit models, and synthesis best practices, this course is ideal for individuals new to FPGA.

Unlock the power of VHDL with our comprehensive training. You'll learn the fundamentals of VHDL syntax, data types, and structural modeling, as well as advanced topics like simulations and testbenches. By the end of this video, you'll be equipped with the knowledge to design, simulate, and implement complex digital systems using VHDL.

Explore the fundamental principles of FPGA resets, understand their real-world applications, and gain insights into different types of resets. Discover how effective reset strategies can enhance system stability and performance in various scenarios, ensuring your systems run smoothly and efficiently.

Get an in-depth understanding of the design and timing constraints methodology in this training course. Explore design constraints entry options, understand design constraints precedence rules and how they impact your design implementation, and learn about the Constraints Propagation Engine (CPE). Get recommendations and tips on what to watch out for when you define your design and timing constraints. Note: This training course specifically refers to Lattice Radiant design software but many of the concepts apply to Lattice Diamond as well.

Learn fundamentals of FPGA configuration and programming in this training course. Here, we focus on the features available on the Nexus FPGAs. Get an in-depth understanding of the configuration flow, explore the status and control registers for configuration status monitoring, and review best practices for configuration debug.

Introducing the advanced security features for configuration that are available on all Lattice Nexus-based FPGAs. Learn how to implement these features through Lattice Radiant design software, including using the Programmer tool, and understanding the options available. Get insights into the lock policies and port locking mechanism to ensure proper usage of these security features.

Join us for an in-depth training course that will provide an extensive exploration of timing constraints in Lattice FPGA design using tools in the Radiant software. This comprehensive session will cover various aspects of timing constraints, including timing basics, static timing analysis, setup and hold times, timing constraint syntaxes, priorities and more. We will delve into the intricacies of timing analysis and demonstrate how to effectively apply timing constraints to optimize FPGA designs for performance and reliability. By the end of this session, you will have the knowledge and skills to leverage timing constraints proficiently in your FPGA projects, ensuring robust and efficient designs.

Learn about the key FPGA architecture differences between the two companies, and explore the unique low power features offered by Lattice. This course will provide you the techniques to convert your designs based on the design flow aspects, which includes selecting an equivalent device, understanding the HDL compatibility, tools comparison, constraints files conversion, and available modes for device programming. GENERAL NOTICE: Other entity and product names used in this publication are for identification purposes only and may be trademarks of their respective holders.

In this course, you will learn about the essential differences in FPGA architecture between two companies. Additionally, you will explore the unique low power features offered by Lattice. The course will equip you with the techniques to convert your designs based on various design flow aspects, including selecting an equivalent device, understanding HDL compatibility, comparing tools, converting constraints files, and identifying available modes for device programming. GENERAL NOTICE: Other entity and product names used in this publication are for identification purposes only and may be trademarks of their respective holders.