The Automate Solution Stack features a reference design that includes a RISC-V processor based subsystem, combined with hardware acceleration that enables flexible, low power and high performance support for multi-channel motor control, with AI-based predictive maintenance over a low-cost, real-time embedded Ethernet Network. This course goes over the full details of the system architecture, operational flow, user interface, and ends with a quick demo of the system.

Learn fundamentals of FPGA configuration and programming in this training course. Here, we focus on the features available on the Nexus FPGAs. Get an in-depth understanding of the configuration flow, explore the status and control registers for configuration status monitoring, and review best practices for configuration debug.

Explore the Lattice iCE40 UltraPlus device architecture. In this course, we step through each and every architecture block, including the PLB, EBR, SPRAM, DSP, PLL, clock network, IO, and the I2C and SPI interface hard IPs. For each block, learn about the features available and the architecture details to help you optimize your design.