382 results found for ""
CertusPro-NX: External Memory Interfaces – Architecture
Advanced
·
12mins
1 Credit
Get to know how to implement the DDR/LPDDR memory interface using all the architecture blocks, the Memory Controller Subsystem, and by ensuring proper initialization and training.
CertusPro-NX: Target Applications
Advanced
·
2mins
1 Credit
Take a look at applications utilizing CertusPro-NX, including designs leveraging the supported external memory interfaces.
CertusPro-NX: External Memory Interfaces Supported
Advanced
·
16mins
1 Credit
Get an introduction to the external memory interfaces supported on the CertusPro-NX FPGA. This module provides an overview and covers the evolution of the DDR/LPDDR features and specifications.
Lattice: Product Portfolio – Control & Security FPGAs Introduction
Basic
·
6mins
Free
Get to know the Control and Security FPGA product portfolio from Lattice.
ModelSim: Simulation Configurations
Intermediate
·
4mins
2 Credit
Learn how you can use simulation configurations to store and invoke VSIM settings to ease future simulation setup.
ModelSim: GUI Layouts
Intermediate
·
3mins
2 Credit
Learn about ModelSim's GUI layout feature, how you can customize the layout, and alternate between different layouts.
ModelSim: Waveform Window Tips
Intermediate
·
13mins
2 Credit
In this module, we share tips for using the ModelSim waveform display to enhance your simulation analysis, including managing signals, cursor usage, and runtime options.
ModelSim: Creating Waveform Scripts
Intermediate
·
3mins
2 Credit
Learn how to create waveform scripts, which can be used to store your customized waveform displays for future use.
ModelSim: Compiling Multiple Files
Intermediate
·
4mins
2 Credit
Learn methods to compile multiple files to speed up your simulation set up.
ModelSim: Creating and Using Custom Libraries
Intermediate
·
5mins
2 Credit
Explore how to create custom libraries and how it can help to simplify future simulations.
ModelSim: Netlist Simulation
Intermediate
·
10mins
2 Credit
Learn how to generate the various netlist files used for FPGA design simulations, including timing simulations.