Double Impact with Avant and Nexus in Industrial Segment 
Basic · 1hr 05mins
Free
This session shares the industrial trends, new application for Avant/ Avant application in  ProAV , medical and T&M. The second part focus on  value selling In the new Application and share success stories from 2022. The presenter shows the industrial trend per region and How we with  Lattice values, features, solutions, and strength.
Using Tools to Drive Success
Basic · 44mins
Free
Design Tools, IP, Boards, and Cables all play an integral role in portraying the overall solution with our class-leading FPGA devices.  In this session, learn how to best utilize Lattice Design Tools to minimize time to start a design and new features to prepare us for the mid-range.  We will share what is happening with our tools currently and in the near future.  We will expose to you the best processes, resources, and options to exhibit Lattice’s commitment to best-in-class Tools and how to procure them.
Taking Nexus to the Next Level
Basic · 45mins
Free
This session takes a comprehensive look at the evolution of the Nexus product portfolio, impactful design-wins, new products to expect in 2023, and the new features that will propel your customer activity to the next level.
The Competitive Landscape
Basic · 36mins
Free
In this session, we will discuss the competitive landscape – from a general market perspective as well as compare and contrast against specific competitors including traditional as well as  new market entrants. We will also provide insight into resources available from Lattice to help you favorably position Lattice products and services against the competition.
Winning with Avant
Basic · 38mins
Free
The mid-range FPGA market provides a large marketplace for Lattice low power and small form factor device design-wins. This session focuses on several mid-range beachhead applications, how to identify the appropriate Avant device, and to help sales with device selection and positioning.
SerDes: Architecture – Introduction
Basic · 8mins
1 Credit
Get an introduction to the basics of Serializers and De-serializers (SerDes), including Lattice's history with SerDes. Learn about the Physical Medium Attachment (PMA) and Physical Coding Sublayer (PCS) blocks, and where they operate in the 7-layer Open Systems Interconnection (OSI) model.
RISC-V: Overview
Basic · 10mins
2 Credit
Get a broad overview of the RISC-V Core IP, including a brief history of RISC-V, where it came from, why it was created, and how it has evolved. This module also includes a list of terminology to help you understand the jargons.
Lattice Avant Platform Overview
Basic · 19mins
Free
Unveiling Lattice Avant, a new FPGA platform purpose-built to bring the Lattice’s power efficient architecture, small size, and performance leadership to mid-range FPGAs. Explore Avant's features, that offer best-in-class power efficiency, advanced connectivity, and optimized compute, all in a small footprint. Find out how the design choices for Avant architecture resulted in power and performance optimizations. Learn about the Avant-E family and portfolio of development tools to get you started on developing with Avant.
Avant: Advantages
Basic · 3mins
Free
Find out how Avant's modernized features are setting it apart from other FPGAs in its class. See how Avant is leading with lower power, smaller footprint, and better performance.
Avant: Features – Low Power Architecture
Basic · 9mins
Free
Discover the design choices for Avant architecture that resulted in power and performance optimizations, including the advantages of going with LUT4 (vs. LUT6) and improved routability.
Avant: Family Plan, Software, IP Support, Development Boards
Basic · 05mins
Free
Learn about the Avant-E family and the rich portfolio of development tools (software, IP, board) to get you started on developing with Avant.
FPGA Design Techniques
Basic · 51mins
1 Credit
Get introduced to different techniques when developing the design that will be implemented in your FPGA. This course covers fundamental concepts, things to watch out for, and provides ideas to optimize your design for speed, area, power, or reliability. Learn about Clock Domain Crossing (CDC) – which is an important consideration when implementing a design in the FPGA – and solutions that can be used to overcome CDC issues. Be guided with best practices to help you design a more stable and optimized FPGA implementation.
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