DFAE Certification 2 (Specialist/Dedicated)

Explore the Lattice CertusPro-NX device architecture. In this course, we step through each and every architecture block, including the PLU, EBR-LRAM, DSP, clock network, IO, and various hard IPs (MIPI D-PHY, PCIe). For each block, learn about the features available and the architecture details to help you optimize your design.

Explore the Lattice CrossLink-NX device architecture. In this course, we step through each and every architecture block, including the PLU, EBR-LRAM, DSP, clock network, IO, and various hard IPs (MIPI D-PHY, PCIe). For each block, learn about the features available and the architecture details to help you optimize your design.

Explore the Lattice iCE40 UltraPlus device architecture. In this course, we step through each and every architecture block, including the PLB, EBR, SPRAM, DSP, PLL, clock network, IO, and the I2C and SPI interface hard IPs. For each block, learn about the features available and the architecture details to help you optimize your design.

Get introduced to different techniques when developing the design that will be implemented in your FPGA. This course covers fundamental concepts, things to watch out for, and provides ideas to optimize your design for speed, area, power, or reliability. Learn about Clock Domain Crossing (CDC) – which is an important consideration when implementing a design in the FPGA – and solutions that can be used to overcome CDC issues. Be guided with best practices to help you design a more stable and optimized FPGA implementation.

In this in-depth course, we will explore Lattice Diamond in greater detail. Get to know each feature and tool more intimately as we unpack various applications of Diamond that can help with your development journey. Explore cross-probing capabilities that make your design inputs more efficient. Verify your design through simulations and on-chip debug. Utilize reports to guide you in optimizing your design. Follow a step-by-step tutorial to get hands-on experience of the full potential of Diamond.

Get an in-depth understanding of the design and timing constraints methodology in this training course. Explore design constraints entry options, understand design constraints precedence rules and how they impact your design implementation, and learn about the Constraints Propagation Engine (CPE). Get recommendations and tips on what to watch out for when you define your design and timing constraints.

Note: This training course specifically refers to Lattice Radiant design software but many of the concepts apply to Lattice Diamond as well.

Learn fundamentals of FPGA configuration and programming in this training course. Here, we focus on the features available on the Nexus FPGAs. Get an in-depth understanding of the configuration flow, explore the status and control registers for configuration status monitoring, and review best practices for configuration debug.

Introducing the advanced security features for configuration that are available on all Lattice Nexus-based FPGAs. Learn how to implement these features through Lattice Radiant design software, including using the Programmer tool, and understanding the options available. Get insights into the lock policies and port locking mechanism to ensure proper usage of these security features.

Get an introduction to the external memory interfaces supported on the CertusPro-NX FPGA. This course starts with an overview of the DDR/LPDDR features and specifications. Then we cover how you can implement the DDR/LPDDR memory interface in your design, using all the architecture blocks, the Memory Controller Subsystem, and by ensuring proper initialization and training.

Introducing the Hardware Checklist, which provides critical hardware implementation recommendations to assist in your FPGA board design. Learn about various considerations as you design a board for your FPGA, such as power design, configuration considerations, and handling sensitive pins.

Note: In this course, we use CertusPro-NX as an example of the FPGA we are designing for. However, the board design and development guidelines apply conceptually to any FPGA board you are developing.