    Synthesis Report
    synthesis:  version Radiant Software (64-bit) 2025.1.1.308.0

    Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
    Copyright (c) 1995 AT&T Corp.   All rights reserved.
    Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
    Copyright (c) 2001 Agere Systems   All rights reserved.
    Copyright (c) 2002-2025 Lattice Semiconductor Corporation,  All rights reserved.
    Wed Nov 12 12:31:49 2025

    Command Line:  C:\lscc\radiant\2025.1\ispfpga\bin\nt64\synthesis.exe -f C:/Users/Mourad Zakhama/Downloads/Lab-Files/Radiant Lab/LAB_01/impl_1/LAB01_impl_1_lattice.synproj -logfile LAB01_impl_1_lattice.srp -gui -msgset C:/Users/Mourad Zakhama/Downloads/Lab-Files/Radiant Lab/LAB_01/promote.xml

    INFO <35002000> - synthesis: Lattice Synthesis Engine launched.

    Synthesis options:
    The -a option is LFCPNX.
    The -t option is CBG256.
    The -sp option is 9_High-Performance_1.0V.
    The -p option is LFCPNX-50.

    ###################### Device Information ######################
    ----------------------------------------------------------------
    Lattice Family        | LFCPNX
    ----------------------------------------------------------------
    Device                | LFCPNX-50
    ----------------------------------------------------------------
    Package               | CBG256
    ----------------------------------------------------------------
    Performance Grade     | 9_High-Performance_1.0V
    ----------------------------------------------------------------
    ################################################################

    ####################### Device Resources #######################
    ----------------------------------------------------------------
    Logic Cells           | 43000
    ----------------------------------------------------------------
    RAM Blocks            | 96
    ----------------------------------------------------------------
    DSP Blocks            | 1287
    ----------------------------------------------------------------
    PLLs                  | 3
    ----------------------------------------------------------------
    I/O Pins              | 161
    ----------------------------------------------------------------
    ################################################################

    Resolving user-selected strategy settings...

    ###################### Strategy Settings #######################
    ----------------------------------------------------------------
    Optimization Goal     | Timing
    ----------------------------------------------------------------
    Top-level Module Name | top
    ----------------------------------------------------------------
    Target Frequency      | 200.000 MHz
    ----------------------------------------------------------------
    Maximum Fanout        | 1000
    ----------------------------------------------------------------
    Timing Path Count     | 3
    ----------------------------------------------------------------
    RAM Read/Write Check  | False
    ----------------------------------------------------------------
    BRAM Utilization      | 100.0%
    ----------------------------------------------------------------
    DSP Usage             | True
    ----------------------------------------------------------------
    DSP Utilization       | 100.0%
    ----------------------------------------------------------------
    FSM Encoding Style    | Auto
    ----------------------------------------------------------------
    Resolve Mixed Drivers | False
    ----------------------------------------------------------------
    Fix Gated Clocks      | True
    ----------------------------------------------------------------
    Mux Style             | Auto
    ----------------------------------------------------------------
    Use Carry Chain       | True
    ----------------------------------------------------------------
    Carry Chain Length    | Infinite
    ----------------------------------------------------------------
    Loop Limit            | 1950
    ----------------------------------------------------------------
    Use I/O Insertion     | True
    ----------------------------------------------------------------
    Use I/O Registers     | False
    ----------------------------------------------------------------
    Resource Sharing      | True
    ----------------------------------------------------------------
    Propagate Constants   | True
    ----------------------------------------------------------------
    Remove Duplicate Reg  | True
    ----------------------------------------------------------------
    Force GSR             | True
    ----------------------------------------------------------------
    ROM Style             | Auto
    ----------------------------------------------------------------
    RAM Style             | Auto
    ----------------------------------------------------------------
    Remove LOC Properties | False
    ----------------------------------------------------------------
    Partition Flow        | False
    ----------------------------------------------------------------
    Use DCC Insertion     | None
    ----------------------------------------------------------------
    ################################################################

    The -comp option is FALSE.
    The -syn option is FALSE.
    Hardtimer checking is enabled (default). The -dt option is not used.

    Output HDL filename: LAB01_impl_1.vm
    -sdc option: SDC file input is LAB01_impl_1_cpe.ldc.
    -path C:/Users/Mourad Zakhama/Downloads/Lab-Files/Radiant Lab/LAB_01 (searchpath added)
    -path C:/Users/Mourad Zakhama/Downloads/Lab-Files/Radiant Lab/LAB_01/PLL01 (searchpath added)
    -path C:/Users/Mourad Zakhama/Downloads/Lab-Files/Radiant Lab/LAB_01/impl_1 (searchpath added)
    -path C:/Users/Mourad Zakhama/Downloads/Lab-Files/Radiant Lab/LAB_01/source/impl_1 (searchpath added)
    -path C:/lscc/radiant/2025.1/ispfpga/jd5d00/data (searchpath added)
    Mixed language design
    Verilog design file: C:/lscc/radiant/2025.1/ip/pmi/pmi_lfcpnx.v
    Verilog design file: C:/Users/Mourad Zakhama/Downloads/Lab-Files/Radiant Lab/LAB_01/PLL01/rtl/PLL01.v
    VHDL library: pmi
    VHDL design file: C:/lscc/radiant/2025.1/ip/pmi/pmi_lfcpnx.vhd
    VHDL library: work
    VHDL design file: C:/Users/Mourad Zakhama/Downloads/Lab-Files/Radiant Lab/LAB_01/source/impl_1/Top.vhd
    WARNING <35935050> - synthesis: input port MBISTCLK is not connected on this instance. VDB-5050

    Compiling design...

    Analyzing Verilog file c:/lscc/radiant/2025.1/ip/pmi/pmi_lfcpnx.v. VERI-1482
    INFO <35901328> - synthesis: c:/lscc/radiant/2025.1/ip/pmi/pmi_lfcpnx.v(1): analyzing included file c:/lscc/radiant/2025.1/ip/pmi/pmi_addsub.v. VERI-1328
    INFO <35901328> - synthesis: c:/lscc/radiant/2025.1/ip/pmi/pmi_addsub.v(40): analyzing included file c:/lscc/radiant/2025.1/ip/pmi/../common/adder_subtractor/rtl/lscc_add_sub.v. VERI-1328
    INFO <35901328> - synthesis: c:/lscc/radiant/2025.1/ip/pmi/pmi_lfcpnx.v(2): analyzing included file c:/lscc/radiant/2025.1/ip/pmi/pmi_add.v. VERI-1328
    INFO <35901328> - synthesis: c:/lscc/radiant/2025.1/ip/pmi/pmi_add.v(50): analyzing included file c:/lscc/radiant/2025.1/ip/pmi/../common/adder/rtl/lscc_adder.v. VERI-1328
    INFO <35901328> - synthesis: c:/lscc/radiant/2025.1/ip/pmi/pmi_lfcpnx.v(3): analyzing included file c:/lscc/radiant/2025.1/ip/pmi/pmi_complex_mult.v. VERI-1328
    INFO <35901328> - synthesis: c:/lscc/radiant/2025.1/ip/pmi/pmi_complex_mult.v(52): analyzing included file c:/lscc/radiant/2025.1/ip/pmi/../common/complex_mult/rtl/lscc_complex_mult.v. VERI-1328
    INFO <35901328> - synthesis: c:/lscc/radiant/2025.1/ip/pmi/pmi_lfcpnx.v(4): analyzing included file c:/lscc/radiant/2025.1/ip/pmi/pmi_counter.v. VERI-1328
    INFO <35901328> - synthesis: c:/lscc/radiant/2025.1/ip/pmi/pmi_counter.v(39): analyzing included file c:/lscc/radiant/2025.1/ip/pmi/../common/counter/rtl/lscc_cntr.v. VERI-1328
    INFO <35901328> - synthesis: c:/lscc/radiant/2025.1/ip/pmi/pmi_lfcpnx.v(5): analyzing included file c:/lscc/radiant/2025.1/ip/pmi/pmi_distributed_dpram.v. VERI-1328
    INFO <35901328> - synthesis: c:/lscc/radiant/2025.1/ip/pmi/pmi_distributed_dpram.v(43): analyzing included file c:/lscc/radiant/2025.1/ip/pmi/../common/distributed_dpram/rtl/lscc_distributed_dpram.v. VERI-1328
    INFO <35901328> - synthesis: c:/lscc/radiant/2025.1/ip/pmi/pmi_lfcpnx.v(6): analyzing included file c:/lscc/radiant/2025.1/ip/pmi/pmi_distributed_spram.v. VERI-1328
    INFO <35901328> - synthesis: c:/lscc/radiant/2025.1/ip/pmi/pmi_distributed_spram.v(42): analyzing included file c:/lscc/radiant/2025.1/ip/pmi/../common/distributed_spram/rtl/lscc_distributed_spram.v. VERI-1328
    INFO <35901328> - synthesis: c:/lscc/radiant/2025.1/ip/pmi/pmi_lfcpnx.v(7): analyzing included file c:/lscc/radiant/2025.1/ip/pmi/pmi_distributed_rom.v. VERI-1328
    INFO <35901328> - synthesis: c:/lscc/radiant/2025.1/ip/pmi/pmi_distributed_rom.v(42): analyzing included file c:/lscc/radiant/2025.1/ip/pmi/../common/distributed_rom/rtl/lscc_distributed_rom.v. VERI-1328
    INFO <35901328> - synthesis: c:/lscc/radiant/2025.1/ip/pmi/pmi_lfcpnx.v(8): analyzing included file c:/lscc/radiant/2025.1/ip/pmi/pmi_distributed_shift_reg.v. VERI-1328
    INFO <35901328> - synthesis: c:/lscc/radiant/2025.1/ip/pmi/pmi_distributed_shift_reg.v(41): analyzing included file c:/lscc/radiant/2025.1/ip/pmi/../common/ram_shift_reg/rtl/lscc_shift_register.v. VERI-1328
    INFO <35901328> - synthesis: c:/lscc/radiant/2025.1/ip/pmi/pmi_lfcpnx.v(9): analyzing included file c:/lscc/radiant/2025.1/ip/pmi/pmi_fifo.v. VERI-1328
    INFO <35901328> - synthesis: c:/lscc/radiant/2025.1/ip/pmi/pmi_fifo.v(44): analyzing included file c:/lscc/radiant/2025.1/ip/pmi/../common/fifo/rtl/lscc_fifo.v. VERI-1328
    INFO <35901328> - synthesis: c:/lscc/radiant/2025.1/ip/pmi/pmi_lfcpnx.v(10): analyzing included file c:/lscc/radiant/2025.1/ip/pmi/pmi_fifo_dc.v. VERI-1328
    INFO <35901328> - synthesis: c:/lscc/radiant/2025.1/ip/pmi/pmi_fifo_dc.v(47): analyzing included file c:/lscc/radiant/2025.1/ip/pmi/../common/fifo_dc/rtl/lscc_fifo_dc.v. VERI-1328
    INFO <35901328> - synthesis: c:/lscc/radiant/2025.1/ip/pmi/pmi_lfcpnx.v(11): analyzing included file c:/lscc/radiant/2025.1/ip/pmi/pmi_mac.v. VERI-1328
    INFO <35901328> - synthesis: c:/lscc/radiant/2025.1/ip/pmi/pmi_mac.v(52): analyzing included file c:/lscc/radiant/2025.1/ip/pmi/../common/mult_accumulate/rtl/lscc_mult_accumulate.v. VERI-1328
    INFO <35901328> - synthesis: c:/lscc/radiant/2025.1/ip/pmi/pmi_lfcpnx.v(12): analyzing included file c:/lscc/radiant/2025.1/ip/pmi/pmi_multaddsubsum.v. VERI-1328
    INFO <35901328> - synthesis: c:/lscc/radiant/2025.1/ip/pmi/pmi_multaddsubsum.v(53): analyzing included file c:/lscc/radiant/2025.1/ip/pmi/../common/mult_add_sub_sum/rtl/lscc_mult_add_sub_sum.v. VERI-1328
    INFO <35901328> - synthesis: c:/lscc/radiant/2025.1/ip/pmi/pmi_lfcpnx.v(13): analyzing included file c:/lscc/radiant/2025.1/ip/pmi/pmi_multaddsub.v. VERI-1328
    INFO <35901328> - synthesis: c:/lscc/radiant/2025.1/ip/pmi/pmi_multaddsub.v(52): analyzing included file c:/lscc/radiant/2025.1/ip/pmi/../common/mult_add_sub/rtl/lscc_mult_add_sub.v. VERI-1328
    INFO <35901328> - synthesis: c:/lscc/radiant/2025.1/ip/pmi/pmi_lfcpnx.v(14): analyzing included file c:/lscc/radiant/2025.1/ip/pmi/pmi_mult.v. VERI-1328
    INFO <35901328> - synthesis: c:/lscc/radiant/2025.1/ip/pmi/pmi_mult.v(51): analyzing included file c:/lscc/radiant/2025.1/ip/pmi/../common/multiplier/rtl/lscc_multiplier.v. VERI-1328
    INFO <35901328> - synthesis: c:/lscc/radiant/2025.1/ip/pmi/pmi_lfcpnx.v(15): analyzing included file c:/lscc/radiant/2025.1/ip/pmi/pmi_ram_dp.v. VERI-1328
    INFO <35901328> - synthesis: c:/lscc/radiant/2025.1/ip/pmi/pmi_ram_dp.v(48): analyzing included file c:/lscc/radiant/2025.1/ip/pmi/../common/ram_dp/rtl/lscc_ram_dp.v. VERI-1328
    INFO <35901328> - synthesis: c:/lscc/radiant/2025.1/ip/pmi/pmi_ram_dp.v(49): analyzing included file c:/lscc/radiant/2025.1/ip/pmi/../LFMXO4/ram_dp/rtl/lscc_lfmxo4_ram_dp.v. VERI-1328
    INFO <35901328> - synthesis: c:/lscc/radiant/2025.1/ip/pmi/pmi_lfcpnx.v(16): analyzing included file c:/lscc/radiant/2025.1/ip/pmi/pmi_ram_dp_be.v. VERI-1328
    INFO <35901328> - synthesis: c:/lscc/radiant/2025.1/ip/pmi/pmi_ram_dp_be.v(49): analyzing included file c:/lscc/radiant/2025.1/ip/pmi/../common/ram_dp/rtl/lscc_ram_dp.v. VERI-1328
    INFO <35901328> - synthesis: c:/lscc/radiant/2025.1/ip/pmi/pmi_ram_dp_be.v(50): analyzing included file c:/lscc/radiant/2025.1/ip/pmi/../LFMXO4/ram_dp/rtl/lscc_lfmxo4_ram_dp.v. VERI-1328
    INFO <35901328> - synthesis: c:/lscc/radiant/2025.1/ip/pmi/pmi_lfcpnx.v(17): analyzing included file c:/lscc/radiant/2025.1/ip/pmi/pmi_ram_dp_true.v. VERI-1328
    INFO <35901328> - synthesis: c:/lscc/radiant/2025.1/ip/pmi/pmi_ram_dp_true.v(49): analyzing included file c:/lscc/radiant/2025.1/ip/pmi/../common/ram_dp_true/rtl/lscc_ram_dp_true.v. VERI-1328
    INFO <35901328> - synthesis: c:/lscc/radiant/2025.1/ip/pmi/pmi_lfcpnx.v(18): analyzing included file c:/lscc/radiant/2025.1/ip/pmi/pmi_ram_dq.v. VERI-1328
    INFO <35901328> - synthesis: c:/lscc/radiant/2025.1/ip/pmi/pmi_ram_dq.v(45): analyzing included file c:/lscc/radiant/2025.1/ip/pmi/../common/ram_dq/rtl/lscc_ram_dq.v. VERI-1328
    INFO <35901328> - synthesis: c:/lscc/radiant/2025.1/ip/pmi/pmi_ram_dq.v(46): analyzing included file c:/lscc/radiant/2025.1/ip/pmi/../LFMXO4/ram_dq/rtl/lscc_lfmxo4_ram_dq.v. VERI-1328
    INFO <35901328> - synthesis: c:/lscc/radiant/2025.1/ip/pmi/pmi_lfcpnx.v(19): analyzing included file c:/lscc/radiant/2025.1/ip/pmi/pmi_ram_dq_be.v. VERI-1328
    INFO <35901328> - synthesis: c:/lscc/radiant/2025.1/ip/pmi/pmi_ram_dq_be.v(45): analyzing included file c:/lscc/radiant/2025.1/ip/pmi/../common/ram_dq/rtl/lscc_ram_dq.v. VERI-1328
    INFO <35901328> - synthesis: c:/lscc/radiant/2025.1/ip/pmi/pmi_ram_dq_be.v(46): analyzing included file c:/lscc/radiant/2025.1/ip/pmi/../LFMXO4/ram_dq/rtl/lscc_lfmxo4_ram_dq.v. VERI-1328
    INFO <35901328> - synthesis: c:/lscc/radiant/2025.1/ip/pmi/pmi_lfcpnx.v(20): analyzing included file c:/lscc/radiant/2025.1/ip/pmi/pmi_rom.v. VERI-1328
    INFO <35901328> - synthesis: c:/lscc/radiant/2025.1/ip/pmi/pmi_rom.v(45): analyzing included file c:/lscc/radiant/2025.1/ip/pmi/../common/rom/rtl/lscc_rom.v. VERI-1328
    INFO <35901328> - synthesis: c:/lscc/radiant/2025.1/ip/pmi/pmi_lfcpnx.v(21): analyzing included file c:/lscc/radiant/2025.1/ip/pmi/pmi_sub.v. VERI-1328
    INFO <35901328> - synthesis: c:/lscc/radiant/2025.1/ip/pmi/pmi_sub.v(50): analyzing included file c:/lscc/radiant/2025.1/ip/pmi/../common/subtractor/rtl/lscc_subtractor.v. VERI-1328
    Analyzing Verilog file c:/users/mourad zakhama/downloads/lab-files/radiant lab/lab_01/pll01/rtl/pll01.v. VERI-1482
    Analyzing VHDL file c:/lscc/radiant/2025.1/ip/pmi/pmi_lfcpnx.vhd. VHDL-1481
    Analyzing VHDL file c:/lscc/radiant/2025.1/ip/pmi/pmi_lfcpnx.vhd

    INFO <35921014> - synthesis: c:/lscc/radiant/2025.1/ip/pmi/pmi_lfcpnx.vhd(4): analyzing package components. VHDL-1014
    Analyzing VHDL file c:/users/mourad zakhama/downloads/lab-files/radiant lab/lab_01/source/impl_1/top.vhd. VHDL-1481
    Analyzing VHDL file c:/users/mourad zakhama/downloads/lab-files/radiant lab/lab_01/source/impl_1/top.vhd

    INFO <35921012> - synthesis: c:/users/mourad zakhama/downloads/lab-files/radiant lab/lab_01/source/impl_1/top.vhd(7): analyzing entity top. VHDL-1012
    INFO <35921010> - synthesis: c:/users/mourad zakhama/downloads/lab-files/radiant lab/lab_01/source/impl_1/top.vhd(17): analyzing architecture behave. VHDL-1010
    INFO <35921504> - synthesis: The default VHDL library search path is now "C:/Users/Mourad Zakhama/Downloads/Lab-Files/Radiant Lab/LAB_01/impl_1". VHDL-1504
    Top module language type = VHDL.
    INFO <35921399> - synthesis: c:/users/mourad zakhama/downloads/lab-files/radiant lab/lab_01/source/impl_1/top.vhd(36): going to verilog side to elaborate module PLL01. VHDL-1399
    INFO <35901018> - synthesis: c:/users/mourad zakhama/downloads/lab-files/radiant lab/lab_01/pll01/rtl/pll01.v(11): compiling module PLL01. VERI-1018
    WARNING <35901214> - synthesis: c:/users/mourad zakhama/downloads/lab-files/radiant lab/lab_01/pll01/rtl/pll01.v(643): assignment to input clki_i. VERI-1214
    INFO <35901018> - synthesis: c:/users/mourad zakhama/downloads/lab-files/radiant lab/lab_01/pll01/rtl/pll01.v(157): compiling module PLL01_ipgen_lscc_pll(FVCO=1600.0,CLKI_FREQ=50.0,CLKOS_PHASE_ACTUAL=90.0,CLKOS_EN=1,FBK_MODE="INTCLKOP",FBCLK_DIVIDER_ACTUAL_STR="2",DIVOP_ACTUAL_STR="15",DIVOS_ACTUAL_STR="15",DIVOS2_ACTUAL_STR="7",DIVOS3_ACTUAL_STR="7",DIVOS4_ACTUAL_STR="7",DIVOS5_ACTUAL_STR="7",SSC_N_CODE_STR="0b000000010",DELA="15",DELB="19",DELC="7",DELD="7",DELE="7",DELF="7",IPI_CMP="0b1100",CSET="8P",CRIPPLE="1P",IPP_CTRL="0b0110",BW_CTL_BIAS="0b1111",V2I_PP_RES="9K"). VERI-1018
    INFO <35901018> - synthesis: C:/lscc/radiant/2025.1/ispfpga/../cae_library/synthesis/verilog/lfcpnx.v(8913): compiling module PLL(BW_CTL_BIAS="0b1111",CRIPPLE="1P",CSET="8P",DELA="15",DELB="19",DELC="7",DELD="7",DELE="7",DELF="7",DIVA="15",DIVB="15",DIVC="7",DIVD="7",DIVE="7",DIVF="7",ENCLK_CLKOP="ENABLED",ENCLK_CLKOS="ENABLED",V2I_1V_EN="ENABLED",FBK_INTEGER_MODE="ENABLED",FBK_MASK="0b00000000",FBK_MMD_DIG="2",IPI_CMP="0b1100",IPP_CTRL="0b0110",K   ....   I_KVCO_SEL="60",V2I_PP_ICTRL="0b11111",V2I_PP_RES="9K",DIV_DEL=72'b01100000110001000110000001100000011000000110001001100010011000100110001,SIM_FLOAT_PRECISION="0.1"). VERI-1018
    INFO <35921400> - synthesis: c:/users/mourad zakhama/downloads/lab-files/radiant lab/lab_01/source/impl_1/top.vhd(36): back to VHDL to continue elaboration. VHDL-1400
    Top module name (VHDL, mixed language): top

    Parameter Setting

    [Parameter Setting Section Start]

    	[Parameter Settings for Instance(s): lscc_pll_inst]
    	(Module: PLL01_ipgen_lscc_pll)
    		FVCO                      1600.000000
    		CLKI_FREQ                 50.000000
    		CLKOP_FREQ_ACTUAL         100.000000
    		CLKOS_FREQ_ACTUAL         100.000000
    		CLKOS2_FREQ_ACTUAL        100.000000
    		CLKOS3_FREQ_ACTUAL        100.000000
    		CLKOS4_FREQ_ACTUAL        100.000000
    		CLKOS5_FREQ_ACTUAL        100.000000
    		CLKOP_PHASE_ACTUAL        0.000000
    		CLKOS_PHASE_ACTUAL        90.000000
    		CLKOS2_PHASE_ACTUAL       0.000000
    		CLKOS3_PHASE_ACTUAL       0.000000
    		CLKOS4_PHASE_ACTUAL       0.000000
    		CLKOS5_PHASE_ACTUAL       0.000000
    		CLKOS_EN                  1
    		CLKOS2_EN                 0
    		CLKOS3_EN                 0
    		CLKOS4_EN                 0
    		CLKOS5_EN                 0
    		CLKOP_BYPASS              0
    		CLKOS_BYPASS              0
    		CLKOS2_BYPASS             0
    		CLKOS3_BYPASS             0
    		CLKOS4_BYPASS             0
    		CLKOS5_BYPASS             0
    		ENCLKOP_EN                0
    		ENCLKOS_EN                0
    		ENCLKOS2_EN               0
    		ENCLKOS3_EN               0
    		ENCLKOS4_EN               0
    		ENCLKOS5_EN               0
    		FRAC_N_EN                 0
    		SS_EN                     0
    		DYN_PORTS_EN              0
    		PLL_RST                   0
    		LOCK_EN                   0
    		PLL_LOCK_STICKY           0
    		LEGACY_EN                 0
    		LMMI_EN                   0
    		APB_EN                    0
    		POWERDOWN_EN              0
    		TRIM_EN_P                 0
    		TRIM_EN_S                 0
    		PLL_REFCLK_FROM_PIN       0
    		IO_TYPE                   "LVDS"
    		CLKOP_TRIM_MODE           "Falling"
    		CLKOS_TRIM_MODE           "Falling"
    		CLKOP_TRIM                "0b0000"
    		CLKOS_TRIM                "0b0000"
    		FBK_MODE                  "INTCLKOP"
    		CLKI_DIVIDER_ACTUAL_STR   "1"
    		FBCLK_DIVIDER_ACTUAL_STR  "2"
    		DIVOP_ACTUAL_STR          "15"
    		DIVOS_ACTUAL_STR          "15"
    		DIVOS2_ACTUAL_STR         "7"
    		DIVOS3_ACTUAL_STR         "7"
    		DIVOS4_ACTUAL_STR         "7"
    		DIVOS5_ACTUAL_STR         "7"
    		SSC_N_CODE_STR            "0b000000010"
    		SSC_F_CODE_STR            "0b000000000000000"
    		SSC_PROFILE               "DOWN"
    		SSC_TBASE_STR             "0b000000000000"
    		SSC_STEP_IN_STR           "0b0000000"
    		SSC_REG_WEIGHTING_SEL_STR "0b000"
    		DELA                      "15"
    		DELB                      "19"
    		DELC                      "7"
    		DELD                      "7"
    		DELE                      "7"
    		DELF                      "7"
    		PHIA                      "0"
    		PHIB                      "0"
    		PHIC                      "0"
    		PHID                      "0"
    		PHIE                      "0"
    		PHIF                      "0"
    		EN_REFCLK_MON             0
    		REF_COUNTS                "0000"
    		INTFBKDEL_SEL             "DISABLED"
    		PMU_WAITFORLOCK           "ENABLED"
    		REF_OSC_CTRL              "3P2"
    		SIM_FLOAT_PRECISION       "0.1"
    		IPI_CMP                   "0b1100"
    		CSET                      "8P"
    		CRIPPLE                   "1P"
    		IPP_CTRL                  "0b0110"
    		IPP_SEL                   "0b1111"
    		BW_CTL_BIAS               "0b1111"
    		V2I_PP_RES                "9K"
    		KP_VCO                    "0b00011"
    		V2I_KVCO_SEL              "60"
    		V2I_1V_EN                 "ENABLED"
    		MAX_STRING_LENGTH         16
    		CONVWIDTH                 32
    		SEL_FBK                   "DIVA"
    		CLKMUX_FB                 "CMUX_CLKOP"
    		SEL_OUTA                  "DISABLED"
    		SEL_OUTB                  "DISABLED"
    		SEL_OUTC                  "DISABLED"
    		SEL_OUTD                  "DISABLED"
    		SEL_OUTE                  "DISABLED"
    		SEL_OUTF                  "DISABLED"
    		REF_INTEGER_MODE          "ENABLED"
    		FBK_INTEGER_MODE          "ENABLED"
    		SSC_EN_SSC                "DISABLED"
    		SSC_EN_SDM                "DISABLED"
    		SSC_ORDER                 "SDM_ORDER1"
    		SSC_DITHER                "DISABLED"
    		SSC_N_CODE                "0b000000000"
    		SSC_F_CODE                "0b000000000000000"
    		SSC_PI_BYPASS             "NOT_BYPASSED"
    		SSC_SQUARE_MODE           "DISABLED"
    		SSC_EN_CENTER_IN          "DOWN_TRIANGLE"
    		SSC_TBASE                 "0b000000000000"
    		SSC_STEP_IN               "0b0000000"
    		SSC_REG_WEIGHTING_SEL     "0b000"
    		ENCLK_CLKOP               "ENABLED"
    		ENCLK_CLKOS               "ENABLED"
    		ENCLK_CLKOS2              "DISABLED"
    		ENCLK_CLKOS3              "DISABLED"
    		ENCLK_CLKOS4              "DISABLED"
    		ENCLK_CLKOS5              "DISABLED"
    		DYN_SOURCE                "STATIC"
    		PLLRESET_ENA              "DISABLED"
    		PLLPDN_EN                 "DISABLED"
    		PLLPD_N                   "USED"
    		LEGACY_ATT                "DISABLED"
    		LDT_LOCK_SEL              "UFREQ"
    		TRIMOP_BYPASS_N           "BYPASSED"
    		TRIMOS_BYPASS_N           "BYPASSED"
    		FBK_MMD_DIG               "2"
    		REF_MMD_DIG               "1"
    		REF_MASK                  "0b00000000"
    		FBK_MASK                  "0b00000000"
    		FBK_MMD_PULS_CTL          "0b0000"
    		FBK_CUR_BLE               "0b00000000"
    		FBK_PI_RC                 "0b1100"
    		FBK_PR_CC                 "0b0000"
    		FBK_PR_IC                 "0b1000"
    		REF_MMD_PULS_CTL          "0b0000"
    		DIVA                      "15"
    		DIVB                      "15"
    		DIVC                      "7"
    		DIVD                      "7"
    		DIVE                      "7"
    		DIVF                      "7"
    		V2I_PP_ICTRL              "0b11111"
    		IPI_CMPN                  "0b0011"
    		FBK_CLK_DIV_O             32'b00000000000000000000000000001111
    		DIV_DEL                   72'b001100000110001000110000001100000011000000110001001100010011000100110001

    	[Parameter Settings for Instance(s): gen_no_refclk_mon.u_PLL]
    	(Module: PLL)
    		BW_CTL_BIAS               "0b1111"
    		CLKOP_TRIM                "0b0000"
    		CLKOS_TRIM                "0b0000"
    		CLKOS2_TRIM               "0b0000"
    		CLKOS3_TRIM               "0b0000"
    		CLKOS4_TRIM               "0b0000"
    		CLKOS5_TRIM               "0b0000"
    		CRIPPLE                   "1P"
    		CSET                      "8P"
    		DELAY_CTRL                "200PS"
    		DELA                      "15"
    		DELB                      "19"
    		DELC                      "7"
    		DELD                      "7"
    		DELE                      "7"
    		DELF                      "7"
    		DIRECTION                 "DISABLED"
    		DIVA                      "15"
    		DIVB                      "15"
    		DIVC                      "7"
    		DIVD                      "7"
    		DIVE                      "7"
    		DIVF                      "7"
    		DYN_SEL                   "0b000"
    		DYN_SOURCE                "STATIC"
    		ENCLK_CLKOP               "ENABLED"
    		ENCLK_CLKOS               "ENABLED"
    		ENCLK_CLKOS2              "DISABLED"
    		ENCLK_CLKOS3              "DISABLED"
    		ENCLK_CLKOS4              "DISABLED"
    		ENCLK_CLKOS5              "DISABLED"
    		ENABLE_SYNC               "DISABLED"
    		FAST_LOCK_EN              "ENABLED"
    		V2I_1V_EN                 "ENABLED"
    		FBK_CUR_BLE               "0b00000000"
    		FBK_EDGE_SEL              "POSITIVE"
    		FBK_IF_TIMING_CTL         "0b00"
    		FBK_INTEGER_MODE          "ENABLED"
    		FBK_MASK                  "0b00000000"
    		FBK_MMD_DIG               "2"
    		FBK_MMD_PULS_CTL          "0b0000"
    		FBK_MODE                  "0b00"
    		FBK_PI_BYPASS             "NOT_BYPASSED"
    		FBK_PI_RC                 "0b1100"
    		FBK_PR_CC                 "0b0000"
    		FBK_PR_IC                 "0b1000"
    		FLOAT_CP                  "DISABLED"
    		FLOCK_CTRL                "2X"
    		FLOCK_EN                  "ENABLED"
    		FLOCK_SRC_SEL             "REFCLK"
    		FORCE_FILTER              "DISABLED"
    		I_CTRL                    "10UA"
    		IPI_CMP                   "0b1100"
    		IPI_CMPN                  "0b0011"
    		IPI_COMP_EN               "DISABLED"
    		IPP_CTRL                  "0b0110"
    		IPP_SEL                   "0b1111"
    		KP_VCO                    "0b00011"
    		LDT_INT_LOCK_STICKY       "DISABLED"
    		LDT_LOCK                  "1536CYC"
    		LDT_LOCK_SEL              "UFREQ"
    		LEGACY_ATT                "DISABLED"
    		LOAD_REG                  "DISABLED"
    		OPENLOOP_EN               "DISABLED"
    		PHIA                      "0"
    		PHIB                      "0"
    		PHIC                      "0"
    		PHID                      "0"
    		PHIE                      "0"
    		PHIF                      "0"
    		PLLPDN_EN                 "DISABLED"
    		PLLPD_N                   "USED"
    		PLLRESET_ENA              "DISABLED"
    		REF_INTEGER_MODE          "ENABLED"
    		REF_MASK                  "0b00000000"
    		REF_MMD_DIG               "1"
    		REF_MMD_IN                "0b00001000"
    		REF_MMD_PULS_CTL          "0b0000"
    		REF_TIMING_CTL            "0b00"
    		REFIN_RESET               "SET"
    		RESET_LF                  "DISABLED"
    		ROTATE                    "DISABLED"
    		SEL_OUTA                  "DISABLED"
    		SEL_OUTB                  "DISABLED"
    		SEL_OUTC                  "DISABLED"
    		SEL_OUTD                  "DISABLED"
    		SEL_OUTE                  "DISABLED"
    		SEL_OUTF                  "DISABLED"
    		SLEEP                     "DISABLED"
    		SSC_DITHER                "DISABLED"
    		SSC_EN_CENTER_IN          "DOWN_TRIANGLE"
    		SSC_EN_SDM                "DISABLED"
    		SSC_EN_SSC                "DISABLED"
    		SSC_F_CODE                "0b000000000000000"
    		SSC_N_CODE                "0b000000000"
    		SSC_ORDER                 "SDM_ORDER1"
    		SSC_PI_BYPASS             "NOT_BYPASSED"
    		SSC_REG_WEIGHTING_SEL     "0b000"
    		SSC_SQUARE_MODE           "DISABLED"
    		SSC_STEP_IN               "0b0000000"
    		SSC_TBASE                 "0b000000000000"
    		STDBY_ATT                 "DISABLED"
    		TRIMOP_BYPASS_N           "BYPASSED"
    		TRIMOS_BYPASS_N           "BYPASSED"
    		TRIMOS2_BYPASS_N          "BYPASSED"
    		TRIMOS3_BYPASS_N          "BYPASSED"
    		TRIMOS4_BYPASS_N          "BYPASSED"
    		TRIMOS5_BYPASS_N          "BYPASSED"
    		V2I_KVCO_SEL              "60"
    		V2I_PP_ICTRL              "0b11111"
    		V2I_PP_RES                "9K"
    		CLKMUX_FB                 "CMUX_CLKOP"
    		SEL_FBK                   "DIVA"
    		DIV_DEL                   72'b001100000110001000110000001100000011000000110001001100010011000100110001
    		PHASE_SEL_DEL             "0b000"
    		PHASE_SEL_DEL_P1          "0b000"
    		EXTERNAL_DIVIDE_FACTOR    "0"
    		INTFBKDEL_SEL             "DISABLED"
    		PMU_WAITFORLOCK           "ENABLED"
    		REF_OSC_CTRL              "3P2"
    		SIM_FLOAT_PRECISION       "0.1"

    [Parameter Setting Section End]

    GSR will not be inferred because no asynchronous signal was found in the netlist.
    Starting design annotation....
    WARNING <70009502> - synthesis: The preferred point for defining clocks is top level ports and driver pins. Pad delays will not be taken into consideration if clocks are defined on nets.
    WARNING <70009502> - synthesis: The preferred point for defining clocks is top level ports and driver pins. Pad delays will not be taken into consideration if clocks are defined on nets.

    Starting full timing analysis...
    Starting design annotation....
    WARNING <70009502> - synthesis: The preferred point for defining clocks is top level ports and driver pins. Pad delays will not be taken into consideration if clocks are defined on nets.
    WARNING <70009502> - synthesis: The preferred point for defining clocks is top level ports and driver pins. Pad delays will not be taken into consideration if clocks are defined on nets.

    Starting full timing analysis...
    Starting design annotation....
    WARNING <70009502> - synthesis: The preferred point for defining clocks is top level ports and driver pins. Pad delays will not be taken into consideration if clocks are defined on nets.
    WARNING <70009502> - synthesis: The preferred point for defining clocks is top level ports and driver pins. Pad delays will not be taken into consideration if clocks are defined on nets.

    Starting full timing analysis...
    Starting design annotation....
    WARNING <70009502> - synthesis: The preferred point for defining clocks is top level ports and driver pins. Pad delays will not be taken into consideration if clocks are defined on nets.
    WARNING <70009502> - synthesis: The preferred point for defining clocks is top level ports and driver pins. Pad delays will not be taken into consideration if clocks are defined on nets.

    Starting full timing analysis...

    Area Report

    ################### Begin Area Report (top)######################
    Number of register bits => 4 of 43000 (0 % )
    FD1P3DX => 4
    GSR => 1
    IB => 3
    LUT4 => 1
    OB => 2
    PLL => 1
    ################### End Area Report ##################
    Number of odd-length carry chains : 0
    Number of even-length carry chains : 0

    Clock Report

    ################### Begin Clock Report ######################
    Clock Nets
    Number of Clocks: 3
      Net : MyPLL/lscc_pll_inst/clk2, loads : 2
      Net : MyPLL/lscc_pll_inst/clk1, loads : 2
      Net : Clk_c, loads : 1
    Clock Enable Nets
    Number of Clock Enables: 1
      Net : VCC_net, loads : 5
    Highest fanout non-clock nets
    Top 10 highest fanout non-clock nets:
      Net : MyPLL/lscc_pll_inst/VCC_net, loads : 9
      Net : VCC_net, loads : 5
      Net : A_Sig, loads : 2
      Net : out2_c_N_1, loads : 2
      Net : A_c, loads : 1
      Net : B_c, loads : 1
      Net : out1_c, loads : 1
      Net : out2_c, loads : 1
      Net : B_sig, loads : 1
      Net : MyPLL/lscc_pll_inst/fbclk_w, loads : 1
    ################### End Clock Report ##################

    Constraint Report

    ################### Begin Constraint Report ######################
    Constraint Summary:
      Total number of constraints: 1
      Total number of constraints dropped: 0
    ###################  End Constraint Report  ######################

    Peak Memory Usage: 404 MB

    --------------------------------------------------------------
    Total CPU Time: 58 secs
    Total REAL Time: 59 secs
    --------------------------------------------------------------
    Checksum -- synthesis -- netlist: e2e147047024a9a99d13964ce23c631af3662b2