
-- VHDL Test Bench Created from source file top.vhd -- Wed Apr 12 15:38:55 2023

--
-- Notes: 
-- 1) This testbench template has been automatically generated using types
-- std_logic and std_logic_vector for the ports of the unit under test.
-- Lattice recommends that these types always be used for the top-level
-- I/O of a design in order to guarantee that the testbench will bind
-- correctly to the timing (post-route) simulation model.
-- 2) To use this template as your testbench, change the filename to any
-- name of your choice with the extension .vhd, and use the "source->import"
-- menu in the ispLEVER Project Navigator to import the testbench.
-- Then edit the user defined section below, adding code to generate the 
-- stimulus for your design.
-- 3) VHDL simulations will produce errors if there are Lattice FPGA library 
-- elements in your design that require the instantiation of GSR, PUR, and
-- TSALL and they are not present in the testbench. For more information see
-- the How To section of online help.  
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY testbench IS
END testbench;

ARCHITECTURE behavior OF testbench IS 

	COMPONENT top
	PORT(
		Clk : IN std_logic;
		En1 : IN std_logic;          
		out2 : OUT std_logic_vector(7 downto 0)
		);
	END COMPONENT;

	SIGNAL Clk :  std_logic:='1';
	SIGNAL En1 :  std_logic;
	SIGNAL out2 :  std_logic_vector(7 downto 0);

BEGIN

-- Please check and add your generic clause manually
	uut: top PORT MAP(
		Clk => Clk,
		En1 => En1,
		out2 => out2
	);


clk <= not clk after 5 ns;

END;
