    Copyright (c) 2002-2022 Lattice Semiconductor Corporation,  All rights reserved.

    Tue Jun  4 10:57:31 2024

    Command Line: par -w -n 1 -t 1 -s 1 -cores 1 -hsp m -exp parPathBased=OFF \
    	lab02_impl_1_map.udb lab02_impl_1.udb

    Cost Table Summary
    Level/       Number       Estimated       Timing       Estimated Worst    Timing          Run      Run
    Cost [udb]   Unrouted     Worst Slack     Score        Slack(hold)        Score(hold)     Time     Status
    ----------   --------     -----------     ------       ---------------    -----------     ----     ------
    5_1   *      0            -               -            -                  -               07       Completed
    * : Design saved.

    Total (real) run time for 1-seed: 8 secs

    par done!

    Lattice Place and Route Report for Design "lab02_impl_1_map.udb"
    Tue Jun  4 10:57:31 2024

    Best Par Run
    PAR: Place And Route Radiant Software (64-bit) 2023.2.1.288.0.
    Command Line: par -w -t 1 -cores 1 -hsp m -exp parPathBased=OFF \
    	lab02_impl_1_map.udb lab02_impl_1_par.dir/5_1.udb

    Loading lab02_impl_1_map.udb ...
    Loading device for application GENERIC from file 'je5d15.nph' in environment: C:/lscc/radiant/2023.2/ispfpga.
    Package Status:                     Final          Version 23.
    Performance Hardware Data Status:   Final          Version 118.1.

    Design:  top
    Family:  LIFCL
    Device:  LIFCL-17
    Package: QFN72
    Performance Grade:   9_High-Performance_1.0V

    Device SLICE utilization summary after final SLICE packing:
       SLICE             13/6912         <1% used

    Number of Signals: 29
    Number of Connections: 49

    Device utilization summary:

       SEIO33                9/39           23% used
                             9/17           53% bonded
       SLICE                13/6912         <1% used
         LUT                10/13824        <1% used
         REG                16/13824        <1% used

    Pin Constraint Summary:
       0 out of 9 pins locked (0% locked).
    .
    Starting Placer Phase 0 (HIER). CPU time: 1 secs , REAL time: 2 secs
    .........
    Finished Placer Phase 0 (HIER). CPU time: 1 secs , REAL time: 2 secs

    Starting Placer Phase 1. CPU time: 1 secs , REAL time: 2 secs
    ..  ..
    ....................

    Placer score = 3347.
    Finished Placer Phase 1. CPU time: 6 secs , REAL time: 7 secs

    Starting Placer Phase 2.
    .

    Placer score =  3249
    Finished Placer Phase 2.  CPU time: 6 secs , REAL time: 7 secs

    Clock Report

    Global Clock Resources:
      CLK_PIN    : 1 out of 13 (7%)
      PLL        : 0 out of 2 (0%)
      DCS        : 0 out of 1 (0%)
      DCC        : 0 out of 62 (0%)
      ECLKDIV    : 0 out of 12 (0%)
      PCLKDIV    : 0 out of 1 (0%)
      OSC        : 0 out of 1 (0%)
      DPHY       : 0 out of 2 (0%)

    Global Clocks:
      PRIMARY "clk_c" from comp "clk" on CLK_PIN site "59 (PT59A)", clk load = 13, ce load = 0, sr load = 0

      PRIMARY  : 1 out of 16 (6%)

    Edge Clocks:

      No edge clock selected.

    I/O Usage Summary (final):
       9 out of 39 (23.1%) SEIO33 sites used.
       9 out of 17 (52.9%) bonded SEIO33 sites used.
       Number of SEIO33 components: 9; differential: 0
       Number of Vref pins used: 0
       0 out of 48 (0.0%) SEIO18 sites used.
       0 out of 22 (0.0%) bonded SEIO18 sites used.
       Number of SEIO18 components: 0; differential: 0
       0 out of 24 (0.0%) DIFFIO18 sites used.
       0 out of 11 (0.0%) bonded DIFFIO18 sites used.
       Number of DIFFIO18 components: 0; differential: 0

    I/O Bank Usage Summary:
    +----------+---------------+------------+------------+------------+
    | I/O Bank | Usage         | Bank Vccio | Bank Vref1 | Bank Vref2 |
    +----------+---------------+------------+------------+------------+
    | 0        | 7 / 10 ( 70%) | 3.3V       | -          | -          |
    | 1        | 2 / 7 ( 28%)  | 3.3V       | -          | -          |
    | 3        | 0 / 12 (  0%) | -          | -          | -          |
    | 5        | 0 / 10 (  0%) | -          | -          | -          |
    +----------+---------------+------------+------------+------------+

    Total Placer CPU time: 6 secs , REAL time: 7 secs

    Checksum -- place: 43dcf4f5374d05a78e2652089ab4ac55500c3cbe
    Writing design to file lab02_impl_1_par.dir/5_1.udb ...

    -----------------------------------------------------------------
    INFO - par: ASE feature is off due to non timing-driven settings.
    -----------------------------------------------------------------

    Start NBR router at 10:57:38 06/04/24

    *****************************************************************
    Info: NBR allows conflicts(one node used by more than one signal)
          in the earlier iterations. In each iteration, it tries to
          solve the conflicts while keeping the critical connections
          routed as short as possible. The routing process is said to
          be completed when no conflicts exist and all connections
          are routed.
    Note: NBR uses a different method to calculate timing slacks. The
          worst slack and total negative slack may not be the same as
          that in timing report. You should always run the timing
          tool to verify your design.
    *****************************************************************

    Starting routing resource preassignment
    Preassignment Summary:
    --------------------------------------------------------------------------------
    12 connections routed with dedicated routing resources
    1 global clock signals routed
    25 connections routed (of 49 total) (51.02%)
    ---------------------------------------------------------
    Clock routing summary:
    Primary clocks (2 used out of 32 available):
        Signal "clk_c" (0, 16)
           Clock   loads: 13    out of    13 routed (100.00%)
    ---------------------------------------------------------
    --------------------------------------------------------------------------------
    Completed routing resource preassignment

    Start NBR section for initial routing at 10:57:38 06/04/24
    Level 4, iteration 1
    +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
    Routing in Serial Mode ......
    +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
    0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; real time: 0 secs

    Info: Initial congestion level at 75.00% usage is 0
    Info: Initial congestion area  at 75.00% usage is 0 (0.00%)

    Start NBR section for normal routing at 10:57:38 06/04/24
    Level 4, iteration 1
    0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; real time: 0 secs

    Start NBR section for post-routing at 10:57:38 06/04/24

    End NBR router with 0 unrouted connection

    Checksum -- route: 1aacf10d58935e0a551439d026130042a48c1a30

    Total CPU time 0 secs
    Total REAL time: 0 secs
    Completely routed.
    End of route.  49 routed (100.00%); 0 unrouted.

    Writing design to file lab02_impl_1_par.dir/5_1.udb ...

    All signals are completely routed.

    PAR_SUMMARY::Run status = Completed
    PAR_SUMMARY::Number of unrouted conns = 0
    PAR_SUMMARY::Estimated worst slack<setup/<ns>> = <n/a>
    PAR_SUMMARY::Timing score<setup/<ns>> = <n/a>
    PAR_SUMMARY::Estimated worst slack<hold/<ns>> = <n/a>
    PAR_SUMMARY::Timing score<hold/<ns>> = <n/a>
    PAR_SUMMARY::Number of errors = 0

    Note: user must run 'timing' for timing closure signoff.

    Total CPU  Time: 7 secs
    Total REAL Time: 8 secs
    Peak Memory Usage: 338.84 MB

    par done!

    Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
    Copyright (c) 1995 AT&T Corp.   All rights reserved.
    Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
    Copyright (c) 2001 Agere Systems   All rights reserved.
    Copyright (c) 2002-2023 Lattice Semiconductor Corporation,  All rights reserved.