-- Library and Use statements for IEEE packages
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;

entity top is
port(
clk   : in  std_logic;
A    : out std_logic_vector (7 downto 0)
);

end top;

architecture behave of top is

signal A_Sig : std_logic_vector (7 downto 0);

begin
process(clk)
begin
if rising_edge(clk) then
	A_sig <= A_sig +1; 
	A <= A_sig;
end if;
end process;



end behave;