    Setting log file to 'C:/Users/Mourad Zakhama/Downloads/Lab-Files/Radiant Lab/LAB_01/impl_1/hdla_gen_hierarchy.html'.
    Starting: parse design source files
    (VHDL-1481) Analyzing VHDL file 'C:/lscc/radiant/2025.1/ispfpga/vhdl_packages/standard.vhd'
    Analyzing VHDL file C:/lscc/radiant/2025.1/ispfpga/vhdl_packages/standard.vhd
    INFO <2046014> - C:/lscc/radiant/2025.1/ispfpga/vhdl_packages/standard.vhd(9,9-9,17) (VHDL-1014) analyzing package 'standard'
    (VHDL-1481) Analyzing VHDL file 'C:/lscc/radiant/2025.1/ispfpga/vhdl_packages/std_1164.vhd'
    Analyzing VHDL file C:/lscc/radiant/2025.1/ispfpga/vhdl_packages/std_1164.vhd
    INFO <2046014> - C:/lscc/radiant/2025.1/ispfpga/vhdl_packages/std_1164.vhd(15,9-15,23) (VHDL-1014) analyzing package 'std_logic_1164'
    INFO <2046013> - C:/lscc/radiant/2025.1/ispfpga/vhdl_packages/std_1164.vhd(178,14-178,28) (VHDL-1013) analyzing package body 'std_logic_1164'
    (VHDL-1481) Analyzing VHDL file 'C:/lscc/radiant/2025.1/ispfpga/vhdl_packages/mgc_qsim.vhd'
    Analyzing VHDL file C:/lscc/radiant/2025.1/ispfpga/vhdl_packages/mgc_qsim.vhd
    INFO <2046014> - C:/lscc/radiant/2025.1/ispfpga/vhdl_packages/mgc_qsim.vhd(18,9-18,19) (VHDL-1014) analyzing package 'qsim_logic'
    INFO <2046013> - C:/lscc/radiant/2025.1/ispfpga/vhdl_packages/mgc_qsim.vhd(753,14-753,24) (VHDL-1013) analyzing package body 'qsim_logic'
    (VHDL-1481) Analyzing VHDL file 'C:/lscc/radiant/2025.1/ispfpga/vhdl_packages/numeric_bit.vhd'
    Analyzing VHDL file C:/lscc/radiant/2025.1/ispfpga/vhdl_packages/numeric_bit.vhd
    INFO <2046014> - C:/lscc/radiant/2025.1/ispfpga/vhdl_packages/numeric_bit.vhd(54,9-54,20) (VHDL-1014) analyzing package 'numeric_bit'
    INFO <2046013> - C:/lscc/radiant/2025.1/ispfpga/vhdl_packages/numeric_bit.vhd(834,14-834,25) (VHDL-1013) analyzing package body 'numeric_bit'
    (VHDL-1481) Analyzing VHDL file 'C:/lscc/radiant/2025.1/ispfpga/vhdl_packages/numeric_std.vhd'
    Analyzing VHDL file C:/lscc/radiant/2025.1/ispfpga/vhdl_packages/numeric_std.vhd
    INFO <2046014> - C:/lscc/radiant/2025.1/ispfpga/vhdl_packages/numeric_std.vhd(57,9-57,20) (VHDL-1014) analyzing package 'numeric_std'
    INFO <2046013> - C:/lscc/radiant/2025.1/ispfpga/vhdl_packages/numeric_std.vhd(874,14-874,25) (VHDL-1013) analyzing package body 'numeric_std'
    (VHDL-1481) Analyzing VHDL file 'C:/lscc/radiant/2025.1/ispfpga/vhdl_packages/textio.vhd'
    Analyzing VHDL file C:/lscc/radiant/2025.1/ispfpga/vhdl_packages/textio.vhd
    INFO <2046014> - C:/lscc/radiant/2025.1/ispfpga/vhdl_packages/textio.vhd(13,9-13,15) (VHDL-1014) analyzing package 'textio'
    INFO <2046013> - C:/lscc/radiant/2025.1/ispfpga/vhdl_packages/textio.vhd(114,14-114,20) (VHDL-1013) analyzing package body 'textio'
    (VHDL-1481) Analyzing VHDL file 'C:/lscc/radiant/2025.1/ispfpga/vhdl_packages/std_logic_textio.vhd'
    Analyzing VHDL file C:/lscc/radiant/2025.1/ispfpga/vhdl_packages/std_logic_textio.vhd
    INFO <2046014> - C:/lscc/radiant/2025.1/ispfpga/vhdl_packages/std_logic_textio.vhd(26,9-26,25) (VHDL-1014) analyzing package 'std_logic_textio'
    INFO <2046013> - C:/lscc/radiant/2025.1/ispfpga/vhdl_packages/std_logic_textio.vhd(72,14-72,30) (VHDL-1013) analyzing package body 'std_logic_textio'
    (VHDL-1481) Analyzing VHDL file 'C:/lscc/radiant/2025.1/ispfpga/vhdl_packages/syn_attr.vhd'
    Analyzing VHDL file C:/lscc/radiant/2025.1/ispfpga/vhdl_packages/syn_attr.vhd
    INFO <2046014> - C:/lscc/radiant/2025.1/ispfpga/vhdl_packages/syn_attr.vhd(39,9-39,19) (VHDL-1014) analyzing package 'attributes'
    (VHDL-1481) Analyzing VHDL file 'C:/lscc/radiant/2025.1/ispfpga/vhdl_packages/syn_misc.vhd'
    Analyzing VHDL file C:/lscc/radiant/2025.1/ispfpga/vhdl_packages/syn_misc.vhd
    INFO <2046014> - C:/lscc/radiant/2025.1/ispfpga/vhdl_packages/syn_misc.vhd(30,9-30,23) (VHDL-1014) analyzing package 'std_logic_misc'
    INFO <2046013> - C:/lscc/radiant/2025.1/ispfpga/vhdl_packages/syn_misc.vhd(182,14-182,28) (VHDL-1013) analyzing package body 'std_logic_misc'
    (VHDL-1481) Analyzing VHDL file 'C:/lscc/radiant/2025.1/ispfpga/vhdl_packages/math_real.vhd'
    INFO <2046014> - ./.__tmp_vxr_0_(56,9-56,18) (VHDL-1014) analyzing package 'math_real'
    INFO <2046013> - ./.__tmp_vxr_0_(685,14-685,23) (VHDL-1013) analyzing package body 'math_real'
    (VHDL-1481) Analyzing VHDL file 'C:/lscc/radiant/2025.1/ispfpga/vhdl_packages/mixed_lang_vltype.vhd'
    Analyzing VHDL file C:/lscc/radiant/2025.1/ispfpga/vhdl_packages/mixed_lang_vltype.vhd
    INFO <2046014> - C:/lscc/radiant/2025.1/ispfpga/vhdl_packages/mixed_lang_vltype.vhd(9,9-9,17) (VHDL-1014) analyzing package 'vl_types'
    INFO <2046013> - C:/lscc/radiant/2025.1/ispfpga/vhdl_packages/mixed_lang_vltype.vhd(88,14-88,22) (VHDL-1013) analyzing package body 'vl_types'
    (VHDL-1481) Analyzing VHDL file 'C:/lscc/radiant/2025.1/ispfpga/vhdl_packages/syn_arit.vhd'
    Analyzing VHDL file C:/lscc/radiant/2025.1/ispfpga/vhdl_packages/syn_arit.vhd
    INFO <2046014> - C:/lscc/radiant/2025.1/ispfpga/vhdl_packages/syn_arit.vhd(25,9-25,24) (VHDL-1014) analyzing package 'std_logic_arith'
    INFO <2046013> - C:/lscc/radiant/2025.1/ispfpga/vhdl_packages/syn_arit.vhd(206,14-206,29) (VHDL-1013) analyzing package body 'std_logic_arith'
    (VHDL-1481) Analyzing VHDL file 'C:/lscc/radiant/2025.1/ispfpga/vhdl_packages/syn_sign.vhd'
    Analyzing VHDL file C:/lscc/radiant/2025.1/ispfpga/vhdl_packages/syn_sign.vhd
    INFO <2046014> - C:/lscc/radiant/2025.1/ispfpga/vhdl_packages/syn_sign.vhd(35,9-35,25) (VHDL-1014) analyzing package 'std_logic_signed'
    INFO <2046013> - C:/lscc/radiant/2025.1/ispfpga/vhdl_packages/syn_sign.vhd(96,14-96,30) (VHDL-1013) analyzing package body 'std_logic_signed'
    (VHDL-1481) Analyzing VHDL file 'C:/lscc/radiant/2025.1/ispfpga/vhdl_packages/syn_unsi.vhd'
    Analyzing VHDL file C:/lscc/radiant/2025.1/ispfpga/vhdl_packages/syn_unsi.vhd
    INFO <2046014> - C:/lscc/radiant/2025.1/ispfpga/vhdl_packages/syn_unsi.vhd(35,9-35,27) (VHDL-1014) analyzing package 'std_logic_unsigned'
    INFO <2046013> - C:/lscc/radiant/2025.1/ispfpga/vhdl_packages/syn_unsi.vhd(94,14-94,32) (VHDL-1013) analyzing package body 'std_logic_unsigned'
    (VHDL-1481) Analyzing VHDL file 'C:/lscc/radiant/2025.1/ispfpga/vhdl_packages/synattr.vhd'
    Analyzing VHDL file C:/lscc/radiant/2025.1/ispfpga/vhdl_packages/synattr.vhd
    INFO <2046014> - C:/lscc/radiant/2025.1/ispfpga/vhdl_packages/synattr.vhd(50,9-50,19) (VHDL-1014) analyzing package 'attributes'
    (VERI-1482) Analyzing Verilog file 'C:/lscc/radiant/2025.1/cae_library/synthesis/verilog/lfcpnx.v'
    (VHDL-1481) Analyzing VHDL file 'C:/lscc/radiant/2025.1/cae_library/synthesis/vhdl/lfcpnx.vhd'
    Analyzing VHDL file C:/lscc/radiant/2025.1/cae_library/synthesis/vhdl/lfcpnx.vhd
    (VHDL-1481) Analyzing VHDL file 'C:/lscc/radiant/2025.1/ip/pmi/pmi_lfcpnx.vhd'
    Analyzing VHDL file C:/lscc/radiant/2025.1/ip/pmi/pmi_lfcpnx.vhd
    (VERI-1482) Analyzing Verilog file 'C:/Users/Mourad Zakhama/Downloads/Lab-Files/Radiant Lab/LAB_01/PLL01/rtl/PLL01.v'
    (VHDL-1481) Analyzing VHDL file 'C:/Users/Mourad Zakhama/Downloads/Lab-Files/Radiant Lab/LAB_01/source/impl_1/Top.vhd'
    Analyzing VHDL file C:/Users/Mourad Zakhama/Downloads/Lab-Files/Radiant Lab/LAB_01/source/impl_1/Top.vhd
    INFO <2046012> - C:/Users/Mourad Zakhama/Downloads/Lab-Files/Radiant Lab/LAB_01/source/impl_1/Top.vhd(7,8-7,11) (VHDL-1012) analyzing entity 'top'
    INFO <2046010> - C:/Users/Mourad Zakhama/Downloads/Lab-Files/Radiant Lab/LAB_01/source/impl_1/Top.vhd(17,14-17,20) (VHDL-1010) analyzing architecture 'behave'
    INFO <2046067> - C:/Users/Mourad Zakhama/Downloads/Lab-Files/Radiant Lab/LAB_01/source/impl_1/Top.vhd(7,8-7,11) (VHDL-1067) elaborating 'top(behave)'
    INFO <2046399> - C:/Users/Mourad Zakhama/Downloads/Lab-Files/Radiant Lab/LAB_01/source/impl_1/Top.vhd(32,1-36,3) (VHDL-1399) switching to Verilog mode to elaborate module 'PLL01'
    INFO <2043018> - C:/Users/Mourad Zakhama/Downloads/Lab-Files/Radiant Lab/LAB_01/PLL01/rtl/PLL01.v(11,8-11,13) (VERI-1018) compiling module 'PLL01_uniq_1'
    INFO <2046400> - C:/Users/Mourad Zakhama/Downloads/Lab-Files/Radiant Lab/LAB_01/source/impl_1/Top.vhd(32,1-36,3) (VHDL-1400) returning to VHDL mode to continue with elaboration
    Done: design load finished with (0) errors, and (0) warnings