-- Library and Use statements for IEEE packages
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;

entity GenCNT is
generic (N : integer := 4);
port(
Clk, CE  : in  std_logic;
CNT : out std_logic_vector (N-1 downto 0)
);

end GenCNT;

architecture behave of GenCNT is

signal CNT2: std_logic_vector (N-1 downto 0):= (others =>'0');

begin

process(CLK)
begin
if rising_edge(clk) then
	if CE='1' then 
		CNT2 <= CNT2 +1;
	else
		CNT2 <= CNT2;
	end if; 

end if; 
CNT <= CNT2;
end process;



end behave;