
module top(	

				datain,
				clkout,
				dataout
			);


  input [7:0] datain;
  output clkout;
  output [7:0] dataout;
  
  reg [7:0] in_reg, out_reg;
  wire clkin;

  my_osc osc_inst (
        .hf_out_en_i(1'b1), 
        .hf_clk_out_o( clkin )
  ) ;
  
  always @(posedge clkin)
	begin
       in_reg <= datain;
	   out_reg <= in_reg;
	end

  assign dataout = out_reg;
  assign clkout = clkin;
endmodule