                             Lattice PAR Report File
    Radiant Software (64-bit) 2025.1.1.308.0
    Wed Nov 12 12:35:01 2025

    Command Line: par -w -n 1 -t 1 -s 1 -cores 1 -hsp m -exp parPathBased=OFF \
    	LAB01_impl_1_map.udb LAB01_impl_1.udb

    Cost Table Summary
    Level/       Number       Estimated       Timing       Estimated Worst    Timing          Run      Run
    Cost [udb]   Unrouted     Worst Slack     Score        Slack(hold)        Score(hold)     Time     Status
    ----------   --------     -----------     ------       ---------------    -----------     ----     ------
    5_1   *      0            -2.070          2070         -                  -               57       Completed
    * : Design saved.

    Total (real) run time for 1-seed: 58 secs

    par done!

    Best Par Run
    PAR: Place And Route Radiant Software (64-bit) 2025.1.1.308.0.
    PARed on: Wed Nov 12 12:35:01 2025

    Command Line: par -w -t 1 -cores 1 -hsp m -exp parPathBased=OFF \
    	LAB01_impl_1_map.udb LAB01_impl_1_par.dir/5_1.udb

    Loading LAB01_impl_1_map.udb ...
    Loading device for application GENERIC from file 'jd5d80.nph' in environment: C:/lscc/radiant/2025.1/ispfpga.
    Package Status:                     Final          Version 16.
    Performance Hardware Data Status:   Final          Version 7.0.

    Design:  top
    Family:  LFCPNX
    Device:  LFCPNX-50
    Package: CBG256
    Performance Grade:   9_High-Performance_1.0V

    Constraint Summary
       Total number of constraints: 12
       Total number of constraints dropped: 0

    Device SLICE utilization summary after final SLICE packing:
       SLICE              6/21500        <1% used

    Number of Signals: 13
    Number of Connections: 70

    Device utilization summary:

       VHI                   1/1           100% used
       SEIO18A               1/132           1% used
                             1/84            1% bonded
       SEIO33                4/159           3% used
                             4/75            5% bonded
       PLL                   1/3            33% used
       SLICE                 6/21500        <1% used
         LUT                 2/43000        <1% used
         REG                 4/43000        <1% used

    Pin Constraint Summary:
       0 out of 5 pins locked (0% locked).

    User does not specify BBOX for group 'FFA', set to size (1x1) internally by PAR.

    User does not specify BBOX for group 'FFB', set to size (1x1) internally by PAR.

    User does not specify BBOX for group 'FFC', set to size (1x1) internally by PAR.

    User does not specify BBOX for group 'FFD', set to size (1x1) internally by PAR.

    .
    Starting Placer Phase 0 (HIER). CPU time: 15 secs , REAL time: 16 secs
    ........
    Finished Placer Phase 0 (HIER). CPU time: 15 secs , REAL time: 16 secs

    User does not specify BBOX for group 'FFA', set to size (1x1) internally by PAR.

    User does not specify BBOX for group 'FFB', set to size (1x1) internally by PAR.

    User does not specify BBOX for group 'FFC', set to size (1x1) internally by PAR.

    User does not specify BBOX for group 'FFD', set to size (1x1) internally by PAR.

    .
    Starting Placer Phase 1. CPU time: 15 secs , REAL time: 16 secs
    ..  ..
    ....................

    Placer score = 47867.
    Finished Placer Phase 1. CPU time: 30 secs , REAL time: 31 secs

    Starting Placer Phase 2.
    .

    Placer score =  47867
    Finished Placer Phase 2.  CPU time: 30 secs , REAL time: 31 secs

    Clock Report

    Global Clock Resources:
      CLK_PIN    : 0 out of 26 (0%)
      PLL        : 1 out of 3 (33%)
      PCS        : 0 out of 1 (0%)
      DCS        : 0 out of 2 (0%)
      DCC        : 0 out of 62 (0%)
      ECLKDIV    : 0 out of 12 (0%)
      PCLKDIV    : 0 out of 2 (0%)
      OSC        : 0 out of 1 (0%)

    Global Clocks:
      PRIMARY "clk1" from CLKOP on comp "MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst" on PLL site "PLL_LLC", clk load = 2, ce load = 0, sr load = 0
      PRIMARY "clk2" from CLKOS on comp "MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst" on PLL site "PLL_LLC", clk load = 2, ce load = 0, sr load = 0

      PRIMARY  : 2 out of 16 (12%)

    Edge Clocks:

      No edge clock selected.

    I/O Usage Summary (final):
       4 out of 159 (2.5%) SEIO33 sites used.
       4 out of 75 (5.3%) bonded SEIO33 sites used.
       Number of SEIO33 components: 4; differential: 0
       Number of Vref pins used: 0
       1 out of 132 (0.8%) SEIO18 sites used.
       1 out of 84 (1.2%) bonded SEIO18 sites used.
       Number of SEIO18 components: 1; differential: 0
       0 out of 66 (0.0%) DIFFIO18 sites used.
       0 out of 42 (0.0%) bonded DIFFIO18 sites used.
       Number of DIFFIO18 components: 0; differential: 0

    I/O Bank Usage Summary:
    +----------+---------------+------------+------------+------------+
    | I/O Bank | Usage         | Bank Vccio | Bank Vref1 | Bank Vref2 |
    +----------+---------------+------------+------------+------------+
    | 0        | 1 / 12 (  8%) | 3.3V       | -          | -          |
    | 1        | 0 / 25 (  0%) | -          | -          | -          |
    | 2        | 2 / 6 ( 33%)  | 3.3V       | -          | -          |
    | 3        | 0 / 24 (  0%) | -          | -          | -          |
    | 4        | 0 / 24 (  0%) | -          | -          | -          |
    | 5        | 1 / 36 (  2%) | 1.8V       | -          | -          |
    | 6        | 0 / 6 (  0%)  | -          | -          | -          |
    | 7        | 1 / 26 (  3%) | 3.3V       | -          | -          |
    +----------+---------------+------------+------------+------------+

    Total Placer CPU time: 30 secs , REAL time: 31 secs

    Checksum -- place: 78485d6be4d002b9f1c489f9baa53762330b4e68
    Writing design to file LAB01_impl_1_par.dir/5_1.udb ...

    Start NBR router at 12:35:33 11/12/25

    *****************************************************************
    Info: NBR allows conflicts(one node used by more than one signal)
          in the earlier iterations. In each iteration, it tries to
          solve the conflicts while keeping the critical connections
          routed as short as possible. The routing process is said to
          be completed when no conflicts exist and all connections
          are routed.
    Note: NBR uses a different method to calculate timing slacks. The
          worst slack and total negative slack may not be the same as
          that in timing report. You should always run the timing
          tool to verify your design.
    *****************************************************************

    Starting routing resource preassignment
    Preassignment Summary:
    --------------------------------------------------------------------------------
    2 connections routed with dedicated routing resources
    2 global clock signals routed
    19 connections routed (of 70 total) (27.14%)
    ---------------------------------------------------------
    Clock routing summary:
    Primary clocks (8 used out of 64 available):
        Signal "clk1" (2, 18, 34, 50)
           Clock   loads: 2     out of     2 routed (100.00%)
        Signal "clk2" (5, 21, 37, 53)
           Clock   loads: 2     out of     2 routed (100.00%)
    Other clocks:
        Signal "VCC_net"
           Clock   loads: 2     out of     2 routed (100.00%)
           Control loads: 2     out of     2 routed (100.00%)
           Data    loads: 9     out of     9 routed (100.00%)
        Signal "MyPLL.lscc_pll_inst.fbclk_w"
           Clock   loads: 1     out of     1 routed (100.00%)
        Signal "Clk_c"
           Clock   loads: 1     out of     1 routed (100.00%)
    ---------------------------------------------------------
    --------------------------------------------------------------------------------
    Completed routing resource preassignment

    Start NBR section for initial routing at 12:35:56 11/12/25
    Level 4, iteration 1
    +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
    Routing in Serial Mode ......
    +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
    0(0.00%) conflict; 0(0.00%) untouched conn; 4139 (nbr) score;
    Estimated worst slack/total negative slack<setup>: -2.070ns/-4.140ns; real time: 25 secs

    Info: Initial congestion level at 75.00% usage is 0
    Info: Initial congestion area  at 75.00% usage is 0 (0.00%)

    Start NBR section for normal routing at 12:35:57 11/12/25
    Level 4, iteration 1
    0(0.00%) conflict; 0(0.00%) untouched conn; 4139 (nbr) score;
    Estimated worst slack/total negative slack<setup>: -2.070ns/-4.140ns; real time: 25 secs

    Start NBR section for post-routing at 12:35:57 11/12/25

    End NBR router with 0 unrouted connection(s)

    Checksum -- route: d26978a686cf4d3036b98780f671bed7737e676f

    Total CPU time 24 secs
    Total REAL time: 25 secs
    Completely routed.
    End of route.  70 routed (100.00%); 0 unrouted.

    Writing design to file LAB01_impl_1_par.dir/5_1.udb ...

    All signals are completely routed.

    PAR_SUMMARY::Run status = Completed
    PAR_SUMMARY::Number of unrouted conns = 0
    PAR_SUMMARY::Estimated worst slack<setup/<ns>> = -2.070
    PAR_SUMMARY::Timing score<setup/<ns>> = 2.070
    PAR_SUMMARY::Estimated worst slack<hold/<ns>> = <n/a>
    PAR_SUMMARY::Timing score<hold/<ns>> = <n/a>
    PAR_SUMMARY::Number of errors = 0

    Note: user must run 'timing' for timing closure signoff.

    Total CPU  Time: 57 secs
    Total REAL Time: 58 secs
    Peak Memory Usage: 1246.90 MB

    par done!

    Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
    Copyright (c) 1995 AT&T Corp.   All rights reserved.
    Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
    Copyright (c) 2001 Agere Systems   All rights reserved.
    Copyright (c) 2002-2025 Lattice Semiconductor Corporation,  All rights reserved.