    Timing Report
    Lattice Timing Report -  Setup  and Hold, Version Radiant Software (64-bit) 2023.2.1.288.0

    Tue Jun  4 10:59:21 2024

    Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
    Copyright (c) 1995 AT&T Corp.   All rights reserved.
    Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
    Copyright (c) 2001 Agere Systems   All rights reserved.
    Copyright (c) 2002-2023 Lattice Semiconductor Corporation,  All rights reserved.

    Command line:    timing -sethld -v 10 -u 10 -endpoints 10 -nperend 1 -html -rpt lab02_impl_1.tws lab02_impl_1_syn.udb -gui -msgset C:/Users/ssyahril/Downloads/FAE_F2F_Training_Labs_V2/FAE_F2F_Training_Labs_V2/LAB_02/promote.xml

    -------------------------------------------
    Design:          top
    Family:          LIFCL
    Device:          LIFCL-17
    Package:         QFN72
    Performance:     9_High-Performance_1.0V
    Package Status:                     Final          Version 23
    -------------------------------------------

    =====================================================================
                        Table of Contents
    =====================================================================
        1  Timing Overview
            1.1  SDC Constraints
            1.2  Constraint Coverage
            1.3  Overall Summary
            1.4  Unconstrained Report
            1.5  Combinational Loop
        2  Setup at Speed Grade 9_High-Performance_1.0V Corner at 85 Degrees
            2.1  Clock Summary
            2.2  Endpoint slacks
            2.3  Detailed Report
        3  Hold at Speed Grade M Corner at 0 Degrees
            3.1  Endpoint slacks
            3.2  Detailed Report

    =====================================================================
                        End of Table of Contents
    =====================================================================

    1  Timing Overview

    1.1  SDC Constraints

    1.2  Constraint Coverage

    Constraint Coverage: 0%

    1.3  Overall Summary

     Setup at Speed Grade 9_High-Performance_1.0V Corner at 85 Degrees    Timing Errors: 0 endpoints;  Total Negative Slack: 0.000 ns
     Hold at Speed Grade M Corner at 0 Degrees                            Timing Errors: 0 endpoints;  Total Negative Slack: 0.000 ns

    1.4  Unconstrained Report

    1.4.1  Unconstrained Start/End Points

    Clocked but unconstrained timing start points
    --------------------------------------------------
    There is no start point satisfying reporting criteria

    Clocked but unconstrained timing end points
    --------------------------------------------------
    There is no end point satisfying reporting criteria

    1.4.2  Start/End Points Without Timing Constraints

    I/O ports without constraint
    ----------------------------
    Possible constraints to use on I/O ports are:
    set_input_delay,
    set_output_delay,
    set_max_delay,
    create_clock,
    create_generated_clock,
    ...

    -------------------------------------------------------------------
         Listing 9 Start or End Points      |           Type
    -------------------------------------------------------------------
    clk                                     |                     input
    A[7]                                    |                    output
    A[6]                                    |                    output
    A[5]                                    |                    output
    A[4]                                    |                    output
    A[3]                                    |                    output
    A[2]                                    |                    output
    A[1]                                    |                    output
    A[0]                                    |                    output
    -------------------------------------------------------------------
                                            |
    Number of I/O ports without constraint  |                         9
                                            |
    -------------------------------------------------------------------

    Nets without clock definition
    Define a clock on a top level port or a generated clock on a clock divider pin associated with this net(s).
    -------------------------------------------------------------------
                Listing 1 Net(s)            |        Source pin
    -------------------------------------------------------------------
    clk_c                                   |         clk_pad.bb_inst/O
    -------------------------------------------------------------------
                                            |
    Number of clock nets without clock defi |
    nition                                  |                         1
                                            |
    -------------------------------------------------------------------

    1.5  Combinational Loop

    None

    2  Setup at Speed Grade 9_High-Performance_1.0V Corner at 85 Degrees
    2.1  Clock Summary

    2.2  Endpoint slacks
    --------------------------------------------------
    There is no end point satisfying reporting criteria

    Total Negative Slack: 0

    2.3  Detailed Report

    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

    Detail report of critical paths

    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

     +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
                        Detailed Report for timing paths
     +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
     +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
                        End of Detailed Report for timing paths
     +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

    ##########################################################

    3  Hold at Speed Grade M Corner at 0 Degrees
    3.1  Endpoint slacks
    --------------------------------------------------
    There is no end point satisfying reporting criteria

    Total Negative Slack: 0

    3.2  Detailed Report

    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

    Detail report of critical paths

    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

     +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
                        Detailed Report for timing paths
     +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
     +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
                        End of Detailed Report for timing paths
     +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

    ##########################################################