                             Lattice Mapping Report File
    Design:  top
    Family:  LFCPNX
    Device:  LFCPNX-50
    Package: CBG256
    Performance Grade:  9_High-Performance_1.0V

    Mapper:    version Radiant Software (64-bit) 2022.1.1.289.4
    Mapped on: Wed Apr 12 09:40:21 2023

    Design Information

    Command line:   map -i LAB01_impl_1_syn.udb -pdc
         D:/02_LSCC/08_TimingConstraint/LAB_01/source/impl_1/MyPDCfile.pdc -o
         LAB01_impl_1_map.udb -mp LAB01_impl_1.mrp -hierrpt -gui

    Design Summary
       Number of registers:           4 out of 43477 (<1%)
          Number of SLICE         registers:    4 out of 43000 (<1%)
          Number of PIO Input     registers:    0 out of   159 (0%)
          Number of PIO Output    registers:    0 out of   159 (0%)
          Number of PIO Tri-State registers:    0 out of   159 (0%)
       Number of LUT4s:               2 out of 43000 (<1%)
          Number used as logic LUT4s:                          2
          Number used as distributed RAM:                      0 (6 per 16X4 RAM)
          Number used as ripple logic:                         0 (2 per CCU2)
       Number of PIOs used/reserved:   12 out of   159 (3%)
          Number of PIOs reserved:      7 (per sysConfig and/or prohibit constraint)
          Number of PIOs used:          5
            Number of PIOs used for single ended IO:         5
            Number of PIO pairs used for differential IO:    0
            Number allocated to regular speed PIOs:     4 out of   75 (5%)
            Number allocated to high speed PIOs:        1 out of   84 (1%)
       Number of Dedicated IO used for ADC/PCS/PCIE:    0 out of   34 (0%)
       Number of IDDR/ODDR/TDDR functions used:      0 out of   402 (0%)
       Number of IOs using at least one DDR function: 0 (0 differential)
       Number of Block RAMs:          0 out of 96 (0%)
       Number of Large RAMs:          0 out of 4 (0%)
       Number of Logical DSP Functions:
          Number of Pre-Adders (9+9):    0 out of 264 (0%)
          Number of Multipliers (18x18): 0 out of 132 (0%)
             Number of 9X9:        0 (1 18x18 = 2   9x9)
             Number of 18x18:      0 (1 18x18 = 1 18x18)
             Number of 18x36:      0 (2 18x18 = 1 18x36)
             Number of 36x36:      0 (4 18x18 = 1 36x36)
          Number of 54-bit Accumulators: 0 out of 66 (0%)
          Number of 18-bit Registers:    0 out of 264 (0%)
       Number of Physical DSP Components:
          Number of PREADD9:             0 out of 264 (0%)
          Number of MULT9:               0 out of 264 (0%)
          Number of MULT18:              0 out of 132 (0%)
          Number of MULT18X36:           0 out of 66 (0%)
          Number of MULT36:              0 out of 33 (0%)
          Number of ACC54:               0 out of 66 (0%)
          Number of REG18:               0 out of 264 (0%)
       Number of ALUREGs:             0 out of 1 (0%)
       Number of PLLs:                1 out of 3 (33%)
       Number of DDRDLLs:             0 out of 2 (0%)

       Number of DLLDELs:             0 out of 10 (0%)
       Number of DQSs:                0 out of 11 (0%)
       Number of DCSs:                0 out of 2 (0%)
       Number of DCCs:                0 out of 62 (0%)
       Number of PCLKDIVs:            0 out of 2 (0%)
       Number of ECLKDIVs:            0 out of 12 (0%)
       Number of ECLKSYNCs:           0 out of 12 (0%)
       Number of ADC Blocks:          0 out of 1 (0%)
       Number of SGMIICDRs:           0 out of 2 (0%)
       Number of PMUs:                0 out of 1 (0%)
       Number of BNKREF18s:           0 out of 3 (0%)
       Number of BNKREF33s:           0 out of 5 (0%)
       Number of I2CFIFOs:            0 out of 1 (0%)
       Number of Oscillators:         0 out of 1 (0%)
       Number of GSR:                 0 out of 1 (0%)
       Number of Cryptographic Block: 0 out of 1 (0%)
       Number of Config IP:           0 out of 1 (0%)
                     TSALL:           0 out of 1 (0%)
       Number of JTAG:                0 out of 1 (0%)
       Number of SED:                 0 out of 1 (0%)
       Number of PCSs:                0 out of 1 (0%)
       Number of PCIE Link Layers:    0 out of 1 (0%)
       Number of Clocks:  3
          Net clk1: 2 loads, 2 rising, 0 falling (Driver: Pin
         MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP)
          Net Clk_c: 1 loads, 1 rising, 0 falling (Driver: Port Clk)
          Net clk2: 2 loads, 2 rising, 0 falling (Driver: Pin
         MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS)
       Number of Clock Enables:  0
       Number of LSRs:  1
          Net VCC_net: 2 loads, 0 SLICEs
       Top 10 highest fanout non-clock nets:
          Net VCC_net: 13 loads
          Net A_Sig: 2 loads
          Net A_c: 1 loads
          Net B_c: 1 loads
          Net B_sig: 1 loads
          Net out1_c: 1 loads
          Net out2_c: 1 loads
          Net out2_N_1: 1 loads

       Number of warnings:  0
       Number of errors:    0

    Design Errors/Warnings

       No errors or warnings present.

    IO (PIO) Attributes

    +---------------------+-----------+-----------+-------+-------+-----------+
    | IO Name             | Direction | Levelmode |  IO   |  IO   | Special   |

    |                     |           |  IO_TYPE  |  REG  |  DDR  | IO Buffer |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | Clk                 | INPUT     |           |       |       |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | out2                | OUTPUT    |           |       |       |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | out1                | OUTPUT    |           |       |       |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | B                   | INPUT     |           |       |       |           |
    +---------------------+-----------+-----------+-------+-------+-----------+
    | A                   | INPUT     |           |       |       |           |
    +---------------------+-----------+-----------+-------+-------+-----------+

    Removed logic

    Block GSR_INST undriven or does not drive anything - clipped.
    Block i15 was optimized away.

    PLL/DLL Summary
    ---------------

    PLL 1:                                 Pin/Node Value
      PLL Instance Name:                            MyPLL/lscc_pll_inst/gen_no_refcl
           k_mon.u_PLL.PLL_inst
      Input Reference Clock:               PIN      Clk_c
      Output Clock(P):                     NODE     clk1
      Output Clock(S):                     NODE     clk2
      Output Clock(S2):                             NONE
      Output Clock(S3):                             NONE
      Output Clock(S4):                             NONE
      Output Clock(S5):                             NONE
      Feedback Signal:                     NODE     clk1
      Reset Signal:                        NODE     GND_net
      Standby Signal:                      NODE     GND_net
      PLL LOCK signal:                              NONE
      PLL Internal LOCK Signal:                     NONE
      A Divider:                                    15
      B Divider:                                    15
      C Divider:                                    7
      D Divider:                                    7
      E Divider:                                    7
      F Divider:                                    7
      A Post Divider Shift:                         15
      B Post Divider Shift:                         19
      C Post Divider Shift:                         7
      D Post Divider Shift:                         7
      E Post Divider Shift:                         7
      F Post Divider Shift:                         7
      A Section VCO Phase Shift:                    0
      B Section VCO Phase Shift:                    0
      C Section VCO Phase Shift:                    0
      D Section VCO Phase Shift:                    0
      E Section VCO Phase Shift:                    0
      F Section VCO Phase Shift:                    0
      CLKOP Trim Setting:                           0000
      CLKOS Trim Setting:                           0000

      CLKOS2 Trim Setting:                          0000
      CLKOS3 Trim Setting:                          0000
      CLKOS4 Trim Setting:                          0000
      CLKOS5 Trim Setting:                          0000

    ASIC Components
    ---------------

    Instance Name: MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst
             Type: PLL_CORE

    Constraint Summary
    ------------------

       Total number of constraints: 11
       Total number of constraints dropped: 0

    Run Time and Memory Usage
    -------------------------

       Total CPU Time: 9 secs
       Total REAL Time: 10 secs
       Peak Memory Usage: 572 MB

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