
module top(	
				clkin,
				datain,
				dataout
			);

  input clkin; 
  input [7:0] datain;
  output [7:0] dataout;
  
  reg [7:0] in_reg, out_reg;

  always @(posedge clkin)
	begin
       in_reg <= datain;
	   out_reg <= in_reg;
	end

  assign dataout = out_reg;
endmodule