// Verilog netlist produced by program LSE 
// Netlist written on Wed Nov 12 12:31:43 2025
// Source file index table: 
// Object locations will have the form @<file_index>(<first_ line>[<left_column>],<last_line>[<right_column>])
// file 0 "c:/lscc/radiant/2025.1/ip/lfmxo4/ram_dp/rtl/lscc_lfmxo4_ram_dp.v"
// file 1 "c:/lscc/radiant/2025.1/ip/lfmxo4/ram_dq/rtl/lscc_lfmxo4_ram_dq.v"
// file 2 "c:/lscc/radiant/2025.1/ip/common/adder/rtl/lscc_adder.v"
// file 3 "c:/lscc/radiant/2025.1/ip/common/adder_subtractor/rtl/lscc_add_sub.v"
// file 4 "c:/lscc/radiant/2025.1/ip/common/complex_mult/rtl/lscc_complex_mult.v"
// file 5 "c:/lscc/radiant/2025.1/ip/common/counter/rtl/lscc_cntr.v"
// file 6 "c:/lscc/radiant/2025.1/ip/common/distributed_dpram/rtl/lscc_distributed_dpram.v"
// file 7 "c:/lscc/radiant/2025.1/ip/common/distributed_rom/rtl/lscc_distributed_rom.v"
// file 8 "c:/lscc/radiant/2025.1/ip/common/distributed_spram/rtl/lscc_distributed_spram.v"
// file 9 "c:/lscc/radiant/2025.1/ip/common/fifo/rtl/lscc_fifo.v"
// file 10 "c:/lscc/radiant/2025.1/ip/common/fifo_dc/rtl/lscc_fifo_dc.v"
// file 11 "c:/lscc/radiant/2025.1/ip/common/mult_accumulate/rtl/lscc_mult_accumulate.v"
// file 12 "c:/lscc/radiant/2025.1/ip/common/mult_add_sub/rtl/lscc_mult_add_sub.v"
// file 13 "c:/lscc/radiant/2025.1/ip/common/mult_add_sub_sum/rtl/lscc_mult_add_sub_sum.v"
// file 14 "c:/lscc/radiant/2025.1/ip/common/multiplier/rtl/lscc_multiplier.v"
// file 15 "c:/lscc/radiant/2025.1/ip/common/ram_dp/rtl/lscc_ram_dp.v"
// file 16 "c:/lscc/radiant/2025.1/ip/common/ram_dp_true/rtl/lscc_ram_dp_true.v"
// file 17 "c:/lscc/radiant/2025.1/ip/common/ram_dq/rtl/lscc_ram_dq.v"
// file 18 "c:/lscc/radiant/2025.1/ip/common/ram_shift_reg/rtl/lscc_shift_register.v"
// file 19 "c:/lscc/radiant/2025.1/ip/common/rom/rtl/lscc_rom.v"
// file 20 "c:/lscc/radiant/2025.1/ip/common/subtractor/rtl/lscc_subtractor.v"
// file 21 "c:/lscc/radiant/2025.1/ip/pmi/pmi_add.v"
// file 22 "c:/lscc/radiant/2025.1/ip/pmi/pmi_addsub.v"
// file 23 "c:/lscc/radiant/2025.1/ip/pmi/pmi_complex_mult.v"
// file 24 "c:/lscc/radiant/2025.1/ip/pmi/pmi_counter.v"
// file 25 "c:/lscc/radiant/2025.1/ip/pmi/pmi_distributed_dpram.v"
// file 26 "c:/lscc/radiant/2025.1/ip/pmi/pmi_distributed_rom.v"
// file 27 "c:/lscc/radiant/2025.1/ip/pmi/pmi_distributed_shift_reg.v"
// file 28 "c:/lscc/radiant/2025.1/ip/pmi/pmi_distributed_spram.v"
// file 29 "c:/lscc/radiant/2025.1/ip/pmi/pmi_fifo.v"
// file 30 "c:/lscc/radiant/2025.1/ip/pmi/pmi_fifo_dc.v"
// file 31 "c:/lscc/radiant/2025.1/ip/pmi/pmi_mac.v"
// file 32 "c:/lscc/radiant/2025.1/ip/pmi/pmi_mult.v"
// file 33 "c:/lscc/radiant/2025.1/ip/pmi/pmi_multaddsub.v"
// file 34 "c:/lscc/radiant/2025.1/ip/pmi/pmi_multaddsubsum.v"
// file 35 "c:/lscc/radiant/2025.1/ip/pmi/pmi_ram_dp.v"
// file 36 "c:/lscc/radiant/2025.1/ip/pmi/pmi_ram_dp_be.v"
// file 37 "c:/lscc/radiant/2025.1/ip/pmi/pmi_ram_dp_true.v"
// file 38 "c:/lscc/radiant/2025.1/ip/pmi/pmi_ram_dq.v"
// file 39 "c:/lscc/radiant/2025.1/ip/pmi/pmi_ram_dq_be.v"
// file 40 "c:/lscc/radiant/2025.1/ip/pmi/pmi_rom.v"
// file 41 "c:/lscc/radiant/2025.1/ip/pmi/pmi_sub.v"
// file 42 "c:/lscc/radiant/2025.1/cae_library/simulation/verilog/lfcpnx/acc54.v"
// file 43 "c:/lscc/radiant/2025.1/cae_library/simulation/verilog/lfcpnx/adc.v"
// file 44 "c:/lscc/radiant/2025.1/cae_library/simulation/verilog/lfcpnx/alureg.v"
// file 45 "c:/lscc/radiant/2025.1/cae_library/simulation/verilog/lfcpnx/bb_adc.v"
// file 46 "c:/lscc/radiant/2025.1/cae_library/simulation/verilog/lfcpnx/bb_cdr.v"
// file 47 "c:/lscc/radiant/2025.1/cae_library/simulation/verilog/lfcpnx/bb_i3c_a.v"
// file 48 "c:/lscc/radiant/2025.1/cae_library/simulation/verilog/lfcpnx/bfd1p3kx.v"
// file 49 "c:/lscc/radiant/2025.1/cae_library/simulation/verilog/lfcpnx/bfd1p3lx.v"
// file 50 "c:/lscc/radiant/2025.1/cae_library/simulation/verilog/lfcpnx/bnkref18.v"
// file 51 "c:/lscc/radiant/2025.1/cae_library/simulation/verilog/lfcpnx/config_ip.v"
// file 52 "c:/lscc/radiant/2025.1/cae_library/simulation/verilog/lfcpnx/config_lmmia.v"
// file 53 "c:/lscc/radiant/2025.1/cae_library/simulation/verilog/lfcpnx/ddrdll.v"
// file 54 "c:/lscc/radiant/2025.1/cae_library/simulation/verilog/lfcpnx/diffclkio.v"
// file 55 "c:/lscc/radiant/2025.1/cae_library/simulation/verilog/lfcpnx/diffio18a.v"
// file 56 "c:/lscc/radiant/2025.1/cae_library/simulation/verilog/lfcpnx/dlldel.v"
// file 57 "c:/lscc/radiant/2025.1/cae_library/simulation/verilog/lfcpnx/dp16k.v"
// file 58 "c:/lscc/radiant/2025.1/cae_library/simulation/verilog/lfcpnx/dpsc512k.v"
// file 59 "c:/lscc/radiant/2025.1/cae_library/simulation/verilog/lfcpnx/dqsbuf.v"
// file 60 "c:/lscc/radiant/2025.1/cae_library/simulation/verilog/lfcpnx/dqsbufa.v"
// file 61 "c:/lscc/radiant/2025.1/cae_library/simulation/verilog/lfcpnx/dqsbuf_ivref.v"
// file 62 "c:/lscc/radiant/2025.1/cae_library/simulation/verilog/lfcpnx/ebr.v"
// file 63 "c:/lscc/radiant/2025.1/cae_library/simulation/verilog/lfcpnx/eclkdiv.v"
// file 64 "c:/lscc/radiant/2025.1/cae_library/simulation/verilog/lfcpnx/eclksync.v"
// file 65 "c:/lscc/radiant/2025.1/cae_library/simulation/verilog/lfcpnx/fifo16k.v"
// file 66 "c:/lscc/radiant/2025.1/cae_library/simulation/verilog/lfcpnx/i2cfifo.v"
// file 67 "c:/lscc/radiant/2025.1/cae_library/simulation/verilog/lfcpnx/ifd1p3bx.v"
// file 68 "c:/lscc/radiant/2025.1/cae_library/simulation/verilog/lfcpnx/ifd1p3dx.v"
// file 69 "c:/lscc/radiant/2025.1/cae_library/simulation/verilog/lfcpnx/ifd1p3ix.v"
// file 70 "c:/lscc/radiant/2025.1/cae_library/simulation/verilog/lfcpnx/ifd1p3jx.v"
// file 71 "c:/lscc/radiant/2025.1/cae_library/simulation/verilog/lfcpnx/jtag.v"
// file 72 "c:/lscc/radiant/2025.1/cae_library/simulation/verilog/lfcpnx/lram.v"
// file 73 "c:/lscc/radiant/2025.1/cae_library/simulation/verilog/lfcpnx/m18x36.v"
// file 74 "c:/lscc/radiant/2025.1/cae_library/simulation/verilog/lfcpnx/mipi.v"
// file 75 "c:/lscc/radiant/2025.1/cae_library/simulation/verilog/lfcpnx/mult18.v"
// file 76 "c:/lscc/radiant/2025.1/cae_library/simulation/verilog/lfcpnx/mult18x18.v"
// file 77 "c:/lscc/radiant/2025.1/cae_library/simulation/verilog/lfcpnx/mult18x36.v"
// file 78 "c:/lscc/radiant/2025.1/cae_library/simulation/verilog/lfcpnx/mult36.v"
// file 79 "c:/lscc/radiant/2025.1/cae_library/simulation/verilog/lfcpnx/mult36x36.v"
// file 80 "c:/lscc/radiant/2025.1/cae_library/simulation/verilog/lfcpnx/mult9.v"
// file 81 "c:/lscc/radiant/2025.1/cae_library/simulation/verilog/lfcpnx/mult9x9.v"
// file 82 "c:/lscc/radiant/2025.1/cae_library/simulation/verilog/lfcpnx/multaddsub18x18.v"
// file 83 "c:/lscc/radiant/2025.1/cae_library/simulation/verilog/lfcpnx/multaddsub18x18wide.v"
// file 84 "c:/lscc/radiant/2025.1/cae_library/simulation/verilog/lfcpnx/multaddsub18x36.v"
// file 85 "c:/lscc/radiant/2025.1/cae_library/simulation/verilog/lfcpnx/multaddsub36x36.v"
// file 86 "c:/lscc/radiant/2025.1/cae_library/simulation/verilog/lfcpnx/multaddsub9x9wide.v"
// file 87 "c:/lscc/radiant/2025.1/cae_library/simulation/verilog/lfcpnx/multiboot.v"
// file 88 "c:/lscc/radiant/2025.1/cae_library/simulation/verilog/lfcpnx/multpreadd18x18.v"
// file 89 "c:/lscc/radiant/2025.1/cae_library/simulation/verilog/lfcpnx/multpreadd9x9.v"
// file 90 "c:/lscc/radiant/2025.1/cae_library/simulation/verilog/lfcpnx/ofd1p3bx.v"
// file 91 "c:/lscc/radiant/2025.1/cae_library/simulation/verilog/lfcpnx/ofd1p3dx.v"
// file 92 "c:/lscc/radiant/2025.1/cae_library/simulation/verilog/lfcpnx/ofd1p3ix.v"
// file 93 "c:/lscc/radiant/2025.1/cae_library/simulation/verilog/lfcpnx/ofd1p3jx.v"
// file 94 "c:/lscc/radiant/2025.1/cae_library/simulation/verilog/lfcpnx/osc.v"
// file 95 "c:/lscc/radiant/2025.1/cae_library/simulation/verilog/lfcpnx/osca.v"
// file 96 "c:/lscc/radiant/2025.1/cae_library/simulation/verilog/lfcpnx/pciell.v"
// file 97 "c:/lscc/radiant/2025.1/cae_library/simulation/verilog/lfcpnx/pcsrefmux.v"
// file 98 "c:/lscc/radiant/2025.1/cae_library/simulation/verilog/lfcpnx/pcsx1.v"
// file 99 "c:/lscc/radiant/2025.1/cae_library/simulation/verilog/lfcpnx/pcsx2.v"
// file 100 "c:/lscc/radiant/2025.1/cae_library/simulation/verilog/lfcpnx/pcsx4.v"
// file 101 "c:/lscc/radiant/2025.1/cae_library/simulation/verilog/lfcpnx/pdp16k.v"
// file 102 "c:/lscc/radiant/2025.1/cae_library/simulation/verilog/lfcpnx/pdpsc16k.v"
// file 103 "c:/lscc/radiant/2025.1/cae_library/simulation/verilog/lfcpnx/pdpsc512k.v"
// file 104 "c:/lscc/radiant/2025.1/cae_library/simulation/verilog/lfcpnx/pll.v"
// file 105 "c:/lscc/radiant/2025.1/cae_library/simulation/verilog/lfcpnx/plla.v"
// file 106 "c:/lscc/radiant/2025.1/cae_library/simulation/verilog/lfcpnx/pllrefcs.v"
// file 107 "c:/lscc/radiant/2025.1/cae_library/simulation/verilog/lfcpnx/pmu.v"
// file 108 "c:/lscc/radiant/2025.1/cae_library/simulation/verilog/lfcpnx/preadd9.v"
// file 109 "c:/lscc/radiant/2025.1/cae_library/simulation/verilog/lfcpnx/refmux.v"
// file 110 "c:/lscc/radiant/2025.1/cae_library/simulation/verilog/lfcpnx/reg18.v"
// file 111 "c:/lscc/radiant/2025.1/cae_library/simulation/verilog/lfcpnx/sedc.v"
// file 112 "c:/lscc/radiant/2025.1/cae_library/simulation/verilog/lfcpnx/seio18a.v"
// file 113 "c:/lscc/radiant/2025.1/cae_library/simulation/verilog/lfcpnx/seio33.v"
// file 114 "c:/lscc/radiant/2025.1/cae_library/simulation/verilog/lfcpnx/sgmiicdr.v"
// file 115 "c:/lscc/radiant/2025.1/cae_library/simulation/verilog/lfcpnx/sp16k.v"
// file 116 "c:/lscc/radiant/2025.1/cae_library/simulation/verilog/lfcpnx/sp512k.v"
// file 117 "c:/lscc/radiant/2025.1/cae_library/simulation/verilog/lfcpnx/tsalla.v"
// file 118 "c:/lscc/radiant/2025.1/cae_library/simulation/verilog/lfcpnx/wdt.v"
// file 119 "c:/lscc/radiant/2025.1/cae_library/simulation/verilog/uaplatform/dpr16x4.v"
// file 120 "c:/lscc/radiant/2025.1/cae_library/simulation/verilog/uaplatform/fd1p3bx.v"
// file 121 "c:/lscc/radiant/2025.1/cae_library/simulation/verilog/uaplatform/fd1p3dx.v"
// file 122 "c:/lscc/radiant/2025.1/cae_library/simulation/verilog/uaplatform/fd1p3ix.v"
// file 123 "c:/lscc/radiant/2025.1/cae_library/simulation/verilog/uaplatform/fd1p3jx.v"
// file 124 "c:/lscc/radiant/2025.1/cae_library/simulation/verilog/uaplatform/gsr.v"
// file 125 "c:/lscc/radiant/2025.1/cae_library/simulation/verilog/uaplatform/ib.v"
// file 126 "c:/lscc/radiant/2025.1/cae_library/simulation/verilog/uaplatform/ob.v"
// file 127 "c:/lscc/radiant/2025.1/cae_library/simulation/verilog/uaplatform/obz.v"
// file 128 "c:/lscc/radiant/2025.1/cae_library/simulation/verilog/uaplatform/pclkdivsp.v"
// file 129 "c:/lscc/radiant/2025.1/cae_library/simulation/verilog/uaplatform/spr16x4.v"
// file 130 "c:/lscc/radiant/2025.1/cae_library/simulation/verilog/uaplatform/widefn9.v"

//
// Verilog Description of module PLL01
// module wrapper written out since it is a black-box. 
//

//

module PLL01 (clki_i, clkop_o, clkos_o) /* synthesis cpe_box=1 */ ;
    input clki_i;
    output clkop_o;
    output clkos_o;
    
    
    
endmodule
