Timing Report
Lattice Timing Report - Setup and Hold, Version Radiant Software (64-bit) 2025.1.1.308.0
Wed Nov 12 12:34:07 2025
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2025 Lattice Semiconductor Corporation, All rights reserved.
Command line: timing -sethld -sp 9_High-Performance_1.0V -hsp m -v 10 -u 10 -endpoints 10 -nperend 1 -html -rpt LAB01_impl_1.tw1 LAB01_impl_1_map.udb -gui -msgset C:/Users/Mourad Zakhama/Downloads/Lab-Files/Radiant Lab/LAB_01/promote.xml
-------------------------------------------
Design: top
Family: LFCPNX
Device: LFCPNX-50
Package: CBG256
Performance: 9_High-Performance_1.0V
Package Status: Final Version 16
Performance Hardware Data Status : Final Version 7.0
-------------------------------------------
=====================================================================
Table of Contents
=====================================================================
1 Timing Overview
1.1 SDC Constraints
1.2 Constraint Coverage
1.3 Overall Summary
1.4 Unconstrained Report
1.5 Combinational Loop
2 Setup at Speed Grade 9_High-Performance_1.0V Corner at 85 Degrees
2.1 Clock Summary
2.2 Endpoint slacks
2.3 Detailed Report
3 Setup at Speed Grade 9_High-Performance_1.0V Corner at 0 Degrees
3.1 Clock Summary
3.2 Endpoint slacks
3.3 Detailed Report
4 Hold at Speed Grade m Corner at 0 Degrees
4.1 Endpoint slacks
4.2 Detailed Report
=====================================================================
End of Table of Contents
=====================================================================
1 Timing Overview
1.1 SDC Constraints
create_generated_clock -name {clk2} -source [get_pins {MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK}] -multiply_by 2 [get_pins {MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS }]
create_generated_clock -name {clk1} -source [get_pins {MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK}] -multiply_by 2 [get_pins {MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP }]
create_clock -name {Clk} -period 20 [get_ports Clk]
1.2 Constraint Coverage
Constraint Coverage: 45.4545%
1.3 Overall Summary
Setup at Speed Grade 9_High-Performance_1.0V Corner at 85 Degrees Timing Errors: 0 endpoints; Total Negative Slack: 0.000 ns
Setup at Speed Grade 9_High-Performance_1.0V Corner at 0 Degrees Timing Errors: 0 endpoints; Total Negative Slack: 0.000 ns
Hold at Speed Grade m Corner at 0 Degrees Timing Errors: 0 endpoints; Total Negative Slack: 0.000 ns
1.4 Unconstrained Report
1.4.1 Unconstrained Start/End Points
Clocked but unconstrained timing start points
-------------------------------------------------------------------
Listing 2 Start Points | Type
-------------------------------------------------------------------
B_sig1.ff_inst/Q | No required time
A_Sig1.ff_inst/Q | No required time
-------------------------------------------------------------------
|
Number of unconstrained timing start po |
ints | 2
|
-------------------------------------------------------------------
Clocked but unconstrained timing end points
-------------------------------------------------------------------
Listing 2 End Points | Type
-------------------------------------------------------------------
A_Sig_c.ff_inst/DF | No arrival time
B_sig_c.ff_inst/DF | No arrival time
-------------------------------------------------------------------
|
Number of unconstrained timing end poin |
ts | 2
|
-------------------------------------------------------------------
1.4.2 Start/End Points Without Timing Constraints
I/O ports without constraint
----------------------------
Possible constraints to use on I/O ports are:
set_input_delay,
set_output_delay,
set_max_delay,
create_clock,
create_generated_clock,
...
-------------------------------------------------------------------
Listing 4 Start or End Points | Type
-------------------------------------------------------------------
A | input
B | input
out1 | output
out2 | output
-------------------------------------------------------------------
|
Number of I/O ports without constraint | 4
|
-------------------------------------------------------------------
Nets without clock definition
Define a clock on a top level port or a generated clock on a clock divider pin associated with this net(s).
--------------------------------------------------
There is no instance satisfying reporting criteria
1.5 Combinational Loop
None
2 Setup at Speed Grade 9_High-Performance_1.0V Corner at 85 Degrees
2.1 Clock Summary
2.1.1 Clock "clk1"
create_generated_clock -name {clk1} -source [get_pins {MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK}] -multiply_by 2 [get_pins {MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP }]
Single Clock Domain
-------------------------------------------------------------------------------------------------------
Clock clk1 | | Period | Frequency
-------------------------------------------------------------------------------------------------------
From clk1 | Target | 10.000 ns | 100.000 MHz
| Actual (all paths) | 2.000 ns | 500.000 MHz
A_Sig_c.ff_inst/CLK (MPW) | (50% duty cycle) | 2.000 ns | 500.000 MHz
-------------------------------------------------------------------------------------------------------
Clock Domain Crossing
------------------------------------------------------------------------------------------------------
Clock clk1 | Worst Time Between Edges | Comment
------------------------------------------------------------------------------------------------------
From clk2 | ---- | No path
From Clk | ---- | No path
------------------------------------------------------------------------------------------------------
2.1.2 Clock "clk2"
create_generated_clock -name {clk2} -source [get_pins {MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK}] -multiply_by 2 [get_pins {MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS }]
Single Clock Domain
-------------------------------------------------------------------------------------------------------
Clock clk2 | | Period | Frequency
-------------------------------------------------------------------------------------------------------
From clk2 | Target | 10.000 ns | 100.000 MHz
| Actual (all paths) | 2.000 ns | 500.000 MHz
B_sig1.ff_inst/CLK (MPW) | (50% duty cycle) | 2.000 ns | 500.000 MHz
-------------------------------------------------------------------------------------------------------
Clock Domain Crossing
------------------------------------------------------------------------------------------------------
Clock clk2 | Worst Time Between Edges | Comment
------------------------------------------------------------------------------------------------------
From clk1 | 2.500 ns | slack = 1.311 ns
From Clk | ---- | No path
------------------------------------------------------------------------------------------------------
2.1.3 Clock "Clk"
create_clock -name {Clk} -period 20 [get_ports Clk]
Single Clock Domain
-------------------------------------------------------------------------------------------------------
Clock Clk | | Period | Frequency
-------------------------------------------------------------------------------------------------------
From Clk | Target | 20.000 ns | 50.000 MHz
| Actual (all paths) | 5.000 ns | 200.000 MHz
Clk_pad.bb_inst/B (MPW) | (50% duty cycle) | 5.000 ns | 200.000 MHz
-------------------------------------------------------------------------------------------------------
Clock Domain Crossing
------------------------------------------------------------------------------------------------------
Clock Clk | Worst Time Between Edges | Comment
------------------------------------------------------------------------------------------------------
From clk1 | ---- | No path
From clk2 | ---- | No path
------------------------------------------------------------------------------------------------------
2.2 Endpoint slacks
-------------------------------------------------------
Listing 2 End Points | Slack
-------------------------------------------------------
B_sig1.ff_inst/DF | 1.311 ns
A_Sig1.ff_inst/DF | 9.324 ns
-------------------------------------------------------
|
Setup # of endpoints with negative slack:| 0
|
-------------------------------------------------------
2.3 Detailed Report
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
Detail report of critical paths
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Detailed Report for timing paths
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++++Path 1 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : A_Sig_c.ff_inst/Q (SLICE)
Path End : B_sig1.ff_inst/DF (SLICE)
Source Clock : clk1 (R)
Destination Clock: clk2 (R)
Logic Level : 2
Delay Ratio : 57.8% (route), 42.2% (logic)
Clock Skew : 0.000 ns
Setup Constraint : 2.500 ns
Common Path Skew : 0.000 ns
Path Slack : 1.311 ns (Passed)
Source Clock Path
<![CDATA[
{
"path_begin":
{
"type":"port",
"log_name":"Clk",
"phy_name":"Clk"
},
"path_end":
{
"type":"pin",
"log_name":"A_Sig_c.ff_inst/CLK",
"phy_name":"A_Sig_c.ff_inst/CLK"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"Clk",
"phy_name":"Clk"
},
"arrive":0.000,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"Clk_pad.bb_inst/B",
"phy_name":"Clk_pad.bb_inst/IOPAD"
},
"pin1":
{
"log_name":"Clk_pad.bb_inst/O",
"phy_name":"Clk_pad.bb_inst/PADDI"
},
"arrive":0.464,
"delay":0.464
},
{
"type":"net_delay",
"net":
{
"log_name":"MyPLL/lscc_pll_inst/Clk_c",
"phy_name":"Clk_c"
},
"arrive":0.764,
"delay":0.300
},
{
"type":"site_delay",
"pin0":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
},
"pin1":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
},
"arrive":0.764,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
},
"pin1":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
},
"arrive":0.764,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"MyPLL/lscc_pll_inst/clk1",
"phy_name":"clk1"
},
"arrive":1.171,
"delay":0.407
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":1.171,
"delay":0.000
}
]
}
]]>
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- -------------- ---------------- --------- --------------------- ------
Clk top CLOCK LATENCY 0.000 0.000 1
Clk NET DELAY 0.000 0.000 1
Clk_pad.bb_inst/B->Clk_pad.bb_inst/O SEIO18A_CORE PADI_DEL 0.464 0.464 1
MyPLL/lscc_pll_inst/Clk_c NET DELAY 0.300 0.764 1
MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP
PLL_CORE 0.000 0.764 2
MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP (TOTAL_ADJUSTMENTS)
PLL_CORE 0.000 0.764 2
MyPLL/lscc_pll_inst/clk1 NET DELAY 0.407 1.171 2
A_Sig_c.ff_inst/CLK CLOCK PIN 0.000 1.171 1
Data Path
<![CDATA[
{
"path_begin":
{
"type":"pin",
"log_name":"A_Sig_c.ff_inst/Q",
"phy_name":"A_Sig_c.ff_inst/Q0"
},
"path_end":
{
"type":"pin",
"log_name":"B_sig1.ff_inst/DF",
"phy_name":"B_sig1.ff_inst/M0"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"A_Sig_c.ff_inst/CLK",
"phy_name":"A_Sig_c.ff_inst/CLK"
},
"pin1":
{
"log_name":"A_Sig_c.ff_inst/Q",
"phy_name":"A_Sig_c.ff_inst/Q0"
},
"arrive":1.475,
"delay":0.304
},
{
"type":"net_delay",
"net":
{
"log_name":"A_Sig",
"phy_name":"A_Sig"
},
"arrive":1.882,
"delay":0.407
},
{
"type":"site_delay",
"pin0":
{
"log_name":"i8_2_lut/B",
"phy_name":"i8_2_lut/B0"
},
"pin1":
{
"log_name":"i8_2_lut/Z",
"phy_name":"i8_2_lut/F0"
},
"arrive":2.095,
"delay":0.213
},
{
"type":"net_delay",
"net":
{
"log_name":"out2_c_N_1",
"phy_name":"out2_c_N_1"
},
"arrive":2.395,
"delay":0.300
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":2.395,
"delay":0.000
}
]
}
]]>
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- -------------- ---------------- --------- --------------------- ------
A_Sig_c.ff_inst/CLK->A_Sig_c.ff_inst/Q SLICE REG_DEL 0.304 1.475 2
A_Sig NET DELAY 0.407 1.882 2
i8_2_lut/B->i8_2_lut/Z SLICE CTOF_DEL 0.213 2.095 1
out2_c_N_1 NET DELAY 0.300 2.395 1
B_sig1.ff_inst/DF ENDPOINT 0.000 2.395 1
Destination Clock Path
<![CDATA[
{
"path_begin":
{
"type":"port",
"log_name":"Clk",
"phy_name":"Clk"
},
"path_end":
{
"type":"pin",
"log_name":"B_sig1.ff_inst/CLK",
"phy_name":"B_sig1.ff_inst/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":2.500,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"Clk",
"phy_name":"Clk"
},
"arrive":2.500,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"Clk_pad.bb_inst/B",
"phy_name":"Clk_pad.bb_inst/IOPAD"
},
"pin1":
{
"log_name":"Clk_pad.bb_inst/O",
"phy_name":"Clk_pad.bb_inst/PADDI"
},
"arrive":2.964,
"delay":0.464
},
{
"type":"net_delay",
"net":
{
"log_name":"MyPLL/lscc_pll_inst/Clk_c",
"phy_name":"Clk_c"
},
"arrive":3.264,
"delay":0.300
},
{
"type":"site_delay",
"pin0":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
},
"pin1":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS"
},
"arrive":3.264,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
},
"pin1":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS"
},
"arrive":3.264,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"MyPLL/lscc_pll_inst/clk2",
"phy_name":"clk2"
},
"arrive":3.671,
"delay":0.407
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":3.671,
"delay":0.000
}
]
}
]]>
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- -------------- ---------------- --------- --------------------- ------
CONSTRAINT 0.000 2.500 1
Clk top CLOCK LATENCY 0.000 2.500 1
Clk NET DELAY 0.000 2.500 1
Clk_pad.bb_inst/B->Clk_pad.bb_inst/O SEIO18A_CORE PADI_DEL 0.464 2.964 1
MyPLL/lscc_pll_inst/Clk_c NET DELAY 0.300 3.264 1
MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS
PLL_CORE 0.000 3.264 2
MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS (TOTAL_ADJUSTMENTS)
PLL_CORE 0.000 3.264 2
MyPLL/lscc_pll_inst/clk2 NET DELAY 0.407 3.671 2
B_sig1.ff_inst/CLK CLOCK PIN 0.000 3.671 1
Uncertainty -(0.000) 3.671
Common Path Skew 0.000 3.671
Setup time -(-0.035) 3.706
---------------------------------------- -------------- ---------------- --------- --------------------- ------
Required Time 3.706
Arrival Time -(2.395)
---------------------------------------- -------------- ---------------- --------- --------------------- ------
Path Slack (Passed) 1.311
++++ Path 2 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : A_Sig_c.ff_inst/Q (SLICE)
Path End : A_Sig1.ff_inst/DF (SLICE)
Source Clock : clk1 (R)
Destination Clock: clk1 (R)
Logic Level : 1
Delay Ratio : 57.2% (route), 42.8% (logic)
Clock Skew : 0.000 ns
Setup Constraint : 10.000 ns
Common Path Skew : 0.000 ns
Path Slack : 9.324 ns (Passed)
Source Clock Path
<![CDATA[
{
"path_begin":
{
"type":"port",
"log_name":"Clk",
"phy_name":"Clk"
},
"path_end":
{
"type":"pin",
"log_name":"A_Sig_c.ff_inst/CLK",
"phy_name":"A_Sig_c.ff_inst/CLK"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"Clk",
"phy_name":"Clk"
},
"arrive":0.000,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"Clk_pad.bb_inst/B",
"phy_name":"Clk_pad.bb_inst/IOPAD"
},
"pin1":
{
"log_name":"Clk_pad.bb_inst/O",
"phy_name":"Clk_pad.bb_inst/PADDI"
},
"arrive":0.464,
"delay":0.464
},
{
"type":"net_delay",
"net":
{
"log_name":"MyPLL/lscc_pll_inst/Clk_c",
"phy_name":"Clk_c"
},
"arrive":0.764,
"delay":0.300
},
{
"type":"site_delay",
"pin0":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
},
"pin1":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
},
"arrive":0.764,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
},
"pin1":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
},
"arrive":0.764,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"MyPLL/lscc_pll_inst/clk1",
"phy_name":"clk1"
},
"arrive":1.171,
"delay":0.407
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":1.171,
"delay":0.000
}
]
}
]]>
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- -------------- ---------------- --------- --------------------- ------
Clk top CLOCK LATENCY 0.000 0.000 1
Clk NET DELAY 0.000 0.000 1
Clk_pad.bb_inst/B->Clk_pad.bb_inst/O SEIO18A_CORE PADI_DEL 0.464 0.464 1
MyPLL/lscc_pll_inst/Clk_c NET DELAY 0.300 0.764 1
MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP
PLL_CORE 0.000 0.764 2
MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP (TOTAL_ADJUSTMENTS)
PLL_CORE 0.000 0.764 2
MyPLL/lscc_pll_inst/clk1 NET DELAY 0.407 1.171 2
A_Sig_c.ff_inst/CLK CLOCK PIN 0.000 1.171 1
Data Path
<![CDATA[
{
"path_begin":
{
"type":"pin",
"log_name":"A_Sig_c.ff_inst/Q",
"phy_name":"A_Sig_c.ff_inst/Q0"
},
"path_end":
{
"type":"pin",
"log_name":"A_Sig1.ff_inst/DF",
"phy_name":"A_Sig1.ff_inst/M0"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"A_Sig_c.ff_inst/CLK",
"phy_name":"A_Sig_c.ff_inst/CLK"
},
"pin1":
{
"log_name":"A_Sig_c.ff_inst/Q",
"phy_name":"A_Sig_c.ff_inst/Q0"
},
"arrive":1.475,
"delay":0.304
},
{
"type":"net_delay",
"net":
{
"log_name":"A_Sig",
"phy_name":"A_Sig"
},
"arrive":1.882,
"delay":0.407
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":1.882,
"delay":0.000
}
]
}
]]>
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- -------------- ---------------- --------- --------------------- ------
A_Sig_c.ff_inst/CLK->A_Sig_c.ff_inst/Q SLICE REG_DEL 0.304 1.475 2
A_Sig NET DELAY 0.407 1.882 2
A_Sig1.ff_inst/DF ENDPOINT 0.000 1.882 1
Destination Clock Path
<![CDATA[
{
"path_begin":
{
"type":"port",
"log_name":"Clk",
"phy_name":"Clk"
},
"path_end":
{
"type":"pin",
"log_name":"A_Sig1.ff_inst/CLK",
"phy_name":"A_Sig1.ff_inst/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":10.000,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"Clk",
"phy_name":"Clk"
},
"arrive":10.000,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"Clk_pad.bb_inst/B",
"phy_name":"Clk_pad.bb_inst/IOPAD"
},
"pin1":
{
"log_name":"Clk_pad.bb_inst/O",
"phy_name":"Clk_pad.bb_inst/PADDI"
},
"arrive":10.464,
"delay":0.464
},
{
"type":"net_delay",
"net":
{
"log_name":"MyPLL/lscc_pll_inst/Clk_c",
"phy_name":"Clk_c"
},
"arrive":10.764,
"delay":0.300
},
{
"type":"site_delay",
"pin0":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
},
"pin1":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
},
"arrive":10.764,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
},
"pin1":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
},
"arrive":10.764,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"MyPLL/lscc_pll_inst/clk1",
"phy_name":"clk1"
},
"arrive":11.171,
"delay":0.407
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":11.171,
"delay":0.000
}
]
}
]]>
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- -------------- ---------------- --------- --------------------- ------
CONSTRAINT 0.000 10.000 1
Clk top CLOCK LATENCY 0.000 10.000 1
Clk NET DELAY 0.000 10.000 1
Clk_pad.bb_inst/B->Clk_pad.bb_inst/O SEIO18A_CORE PADI_DEL 0.464 10.464 1
MyPLL/lscc_pll_inst/Clk_c NET DELAY 0.300 10.764 1
MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP
PLL_CORE 0.000 10.764 2
MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP (TOTAL_ADJUSTMENTS)
PLL_CORE 0.000 10.764 2
MyPLL/lscc_pll_inst/clk1 NET DELAY 0.407 11.171 2
A_Sig1.ff_inst/CLK CLOCK PIN 0.000 11.171 1
Uncertainty -(0.000) 11.171
Common Path Skew 0.000 11.171
Setup time -(-0.035) 11.206
---------------------------------------- -------------- ---------------- --------- --------------------- ------
Required Time 11.206
Arrival Time -(1.882)
---------------------------------------- -------------- ---------------- --------- --------------------- ------
Path Slack (Passed) 9.324
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
End of Detailed Report for timing paths
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
##########################################################
3 Setup at Speed Grade 9_High-Performance_1.0V Corner at 0 Degrees
3.1 Clock Summary
3.1.1 Clock "clk1"
create_generated_clock -name {clk1} -source [get_pins {MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK}] -multiply_by 2 [get_pins {MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP }]
Single Clock Domain
-------------------------------------------------------------------------------------------------------
Clock clk1 | | Period | Frequency
-------------------------------------------------------------------------------------------------------
From clk1 | Target | 10.000 ns | 100.000 MHz
| Actual (all paths) | 2.000 ns | 500.000 MHz
A_Sig_c.ff_inst/CLK (MPW) | (50% duty cycle) | 2.000 ns | 500.000 MHz
-------------------------------------------------------------------------------------------------------
Clock Domain Crossing
------------------------------------------------------------------------------------------------------
Clock clk1 | Worst Time Between Edges | Comment
------------------------------------------------------------------------------------------------------
From clk2 | ---- | No path
From Clk | ---- | No path
------------------------------------------------------------------------------------------------------
3.1.2 Clock "clk2"
create_generated_clock -name {clk2} -source [get_pins {MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK}] -multiply_by 2 [get_pins {MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS }]
Single Clock Domain
-------------------------------------------------------------------------------------------------------
Clock clk2 | | Period | Frequency
-------------------------------------------------------------------------------------------------------
From clk2 | Target | 10.000 ns | 100.000 MHz
| Actual (all paths) | 2.000 ns | 500.000 MHz
B_sig1.ff_inst/CLK (MPW) | (50% duty cycle) | 2.000 ns | 500.000 MHz
-------------------------------------------------------------------------------------------------------
Clock Domain Crossing
------------------------------------------------------------------------------------------------------
Clock clk2 | Worst Time Between Edges | Comment
------------------------------------------------------------------------------------------------------
From clk1 | 2.500 ns | slack = 1.310 ns
From Clk | ---- | No path
------------------------------------------------------------------------------------------------------
3.1.3 Clock "Clk"
create_clock -name {Clk} -period 20 [get_ports Clk]
Single Clock Domain
-------------------------------------------------------------------------------------------------------
Clock Clk | | Period | Frequency
-------------------------------------------------------------------------------------------------------
From Clk | Target | 20.000 ns | 50.000 MHz
| Actual (all paths) | 5.000 ns | 200.000 MHz
Clk_pad.bb_inst/B (MPW) | (50% duty cycle) | 5.000 ns | 200.000 MHz
-------------------------------------------------------------------------------------------------------
Clock Domain Crossing
------------------------------------------------------------------------------------------------------
Clock Clk | Worst Time Between Edges | Comment
------------------------------------------------------------------------------------------------------
From clk1 | ---- | No path
From clk2 | ---- | No path
------------------------------------------------------------------------------------------------------
3.2 Endpoint slacks
-------------------------------------------------------
Listing 2 End Points | Slack
-------------------------------------------------------
B_sig1.ff_inst/DF | 1.310 ns
A_Sig1.ff_inst/DF | 9.323 ns
-------------------------------------------------------
|
Setup # of endpoints with negative slack:| 0
|
-------------------------------------------------------
3.3 Detailed Report
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
Detail report of critical paths
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Detailed Report for timing paths
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++++Path 1 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : A_Sig_c.ff_inst/Q (SLICE)
Path End : B_sig1.ff_inst/DF (SLICE)
Source Clock : clk1 (R)
Destination Clock: clk2 (R)
Logic Level : 2
Delay Ratio : 57.7% (route), 42.3% (logic)
Clock Skew : 0.000 ns
Setup Constraint : 2.500 ns
Common Path Skew : 0.000 ns
Path Slack : 1.310 ns (Passed)
Source Clock Path
<![CDATA[
{
"path_begin":
{
"type":"port",
"log_name":"Clk",
"phy_name":"Clk"
},
"path_end":
{
"type":"pin",
"log_name":"A_Sig_c.ff_inst/CLK",
"phy_name":"A_Sig_c.ff_inst/CLK"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"Clk",
"phy_name":"Clk"
},
"arrive":0.000,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"Clk_pad.bb_inst/B",
"phy_name":"Clk_pad.bb_inst/IOPAD"
},
"pin1":
{
"log_name":"Clk_pad.bb_inst/O",
"phy_name":"Clk_pad.bb_inst/PADDI"
},
"arrive":0.440,
"delay":0.440
},
{
"type":"net_delay",
"net":
{
"log_name":"MyPLL/lscc_pll_inst/Clk_c",
"phy_name":"Clk_c"
},
"arrive":0.740,
"delay":0.300
},
{
"type":"site_delay",
"pin0":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
},
"pin1":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
},
"arrive":0.740,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
},
"pin1":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
},
"arrive":0.740,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"MyPLL/lscc_pll_inst/clk1",
"phy_name":"clk1"
},
"arrive":1.147,
"delay":0.407
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":1.147,
"delay":0.000
}
]
}
]]>
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- -------------- ---------------- --------- --------------------- ------
Clk top CLOCK LATENCY 0.000 0.000 1
Clk NET DELAY 0.000 0.000 1
Clk_pad.bb_inst/B->Clk_pad.bb_inst/O SEIO18A_CORE PADI_DEL 0.440 0.440 1
MyPLL/lscc_pll_inst/Clk_c NET DELAY 0.300 0.740 1
MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP
PLL_CORE 0.000 0.740 2
MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP (TOTAL_ADJUSTMENTS)
PLL_CORE 0.000 0.740 2
MyPLL/lscc_pll_inst/clk1 NET DELAY 0.407 1.147 2
A_Sig_c.ff_inst/CLK CLOCK PIN 0.000 1.147 1
Data Path
<![CDATA[
{
"path_begin":
{
"type":"pin",
"log_name":"A_Sig_c.ff_inst/Q",
"phy_name":"A_Sig_c.ff_inst/Q0"
},
"path_end":
{
"type":"pin",
"log_name":"B_sig1.ff_inst/DF",
"phy_name":"B_sig1.ff_inst/M0"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"A_Sig_c.ff_inst/CLK",
"phy_name":"A_Sig_c.ff_inst/CLK"
},
"pin1":
{
"log_name":"A_Sig_c.ff_inst/Q",
"phy_name":"A_Sig_c.ff_inst/Q0"
},
"arrive":1.452,
"delay":0.305
},
{
"type":"net_delay",
"net":
{
"log_name":"A_Sig",
"phy_name":"A_Sig"
},
"arrive":1.859,
"delay":0.407
},
{
"type":"site_delay",
"pin0":
{
"log_name":"i8_2_lut/B",
"phy_name":"i8_2_lut/B0"
},
"pin1":
{
"log_name":"i8_2_lut/Z",
"phy_name":"i8_2_lut/F0"
},
"arrive":2.072,
"delay":0.213
},
{
"type":"net_delay",
"net":
{
"log_name":"out2_c_N_1",
"phy_name":"out2_c_N_1"
},
"arrive":2.372,
"delay":0.300
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":2.372,
"delay":0.000
}
]
}
]]>
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- -------------- ---------------- --------- --------------------- ------
A_Sig_c.ff_inst/CLK->A_Sig_c.ff_inst/Q SLICE REG_DEL 0.305 1.452 2
A_Sig NET DELAY 0.407 1.859 2
i8_2_lut/B->i8_2_lut/Z SLICE CTOF_DEL 0.213 2.072 1
out2_c_N_1 NET DELAY 0.300 2.372 1
B_sig1.ff_inst/DF ENDPOINT 0.000 2.372 1
Destination Clock Path
<![CDATA[
{
"path_begin":
{
"type":"port",
"log_name":"Clk",
"phy_name":"Clk"
},
"path_end":
{
"type":"pin",
"log_name":"B_sig1.ff_inst/CLK",
"phy_name":"B_sig1.ff_inst/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":2.500,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"Clk",
"phy_name":"Clk"
},
"arrive":2.500,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"Clk_pad.bb_inst/B",
"phy_name":"Clk_pad.bb_inst/IOPAD"
},
"pin1":
{
"log_name":"Clk_pad.bb_inst/O",
"phy_name":"Clk_pad.bb_inst/PADDI"
},
"arrive":2.940,
"delay":0.440
},
{
"type":"net_delay",
"net":
{
"log_name":"MyPLL/lscc_pll_inst/Clk_c",
"phy_name":"Clk_c"
},
"arrive":3.240,
"delay":0.300
},
{
"type":"site_delay",
"pin0":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
},
"pin1":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS"
},
"arrive":3.240,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
},
"pin1":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS"
},
"arrive":3.240,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"MyPLL/lscc_pll_inst/clk2",
"phy_name":"clk2"
},
"arrive":3.647,
"delay":0.407
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":3.647,
"delay":0.000
}
]
}
]]>
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- -------------- ---------------- --------- --------------------- ------
CONSTRAINT 0.000 2.500 1
Clk top CLOCK LATENCY 0.000 2.500 1
Clk NET DELAY 0.000 2.500 1
Clk_pad.bb_inst/B->Clk_pad.bb_inst/O SEIO18A_CORE PADI_DEL 0.440 2.940 1
MyPLL/lscc_pll_inst/Clk_c NET DELAY 0.300 3.240 1
MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS
PLL_CORE 0.000 3.240 2
MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS (TOTAL_ADJUSTMENTS)
PLL_CORE 0.000 3.240 2
MyPLL/lscc_pll_inst/clk2 NET DELAY 0.407 3.647 2
B_sig1.ff_inst/CLK CLOCK PIN 0.000 3.647 1
Uncertainty -(0.000) 3.647
Common Path Skew 0.000 3.647
Setup time -(-0.035) 3.682
---------------------------------------- -------------- ---------------- --------- --------------------- ------
Required Time 3.682
Arrival Time -(2.372)
---------------------------------------- -------------- ---------------- --------- --------------------- ------
Path Slack (Passed) 1.310
++++ Path 2 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : A_Sig_c.ff_inst/Q (SLICE)
Path End : A_Sig1.ff_inst/DF (SLICE)
Source Clock : clk1 (R)
Destination Clock: clk1 (R)
Logic Level : 1
Delay Ratio : 57.2% (route), 42.8% (logic)
Clock Skew : 0.000 ns
Setup Constraint : 10.000 ns
Common Path Skew : 0.000 ns
Path Slack : 9.323 ns (Passed)
Source Clock Path
<![CDATA[
{
"path_begin":
{
"type":"port",
"log_name":"Clk",
"phy_name":"Clk"
},
"path_end":
{
"type":"pin",
"log_name":"A_Sig_c.ff_inst/CLK",
"phy_name":"A_Sig_c.ff_inst/CLK"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"Clk",
"phy_name":"Clk"
},
"arrive":0.000,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"Clk_pad.bb_inst/B",
"phy_name":"Clk_pad.bb_inst/IOPAD"
},
"pin1":
{
"log_name":"Clk_pad.bb_inst/O",
"phy_name":"Clk_pad.bb_inst/PADDI"
},
"arrive":0.440,
"delay":0.440
},
{
"type":"net_delay",
"net":
{
"log_name":"MyPLL/lscc_pll_inst/Clk_c",
"phy_name":"Clk_c"
},
"arrive":0.740,
"delay":0.300
},
{
"type":"site_delay",
"pin0":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
},
"pin1":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
},
"arrive":0.740,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
},
"pin1":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
},
"arrive":0.740,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"MyPLL/lscc_pll_inst/clk1",
"phy_name":"clk1"
},
"arrive":1.147,
"delay":0.407
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":1.147,
"delay":0.000
}
]
}
]]>
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- -------------- ---------------- --------- --------------------- ------
Clk top CLOCK LATENCY 0.000 0.000 1
Clk NET DELAY 0.000 0.000 1
Clk_pad.bb_inst/B->Clk_pad.bb_inst/O SEIO18A_CORE PADI_DEL 0.440 0.440 1
MyPLL/lscc_pll_inst/Clk_c NET DELAY 0.300 0.740 1
MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP
PLL_CORE 0.000 0.740 2
MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP (TOTAL_ADJUSTMENTS)
PLL_CORE 0.000 0.740 2
MyPLL/lscc_pll_inst/clk1 NET DELAY 0.407 1.147 2
A_Sig_c.ff_inst/CLK CLOCK PIN 0.000 1.147 1
Data Path
<![CDATA[
{
"path_begin":
{
"type":"pin",
"log_name":"A_Sig_c.ff_inst/Q",
"phy_name":"A_Sig_c.ff_inst/Q0"
},
"path_end":
{
"type":"pin",
"log_name":"A_Sig1.ff_inst/DF",
"phy_name":"A_Sig1.ff_inst/M0"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"A_Sig_c.ff_inst/CLK",
"phy_name":"A_Sig_c.ff_inst/CLK"
},
"pin1":
{
"log_name":"A_Sig_c.ff_inst/Q",
"phy_name":"A_Sig_c.ff_inst/Q0"
},
"arrive":1.452,
"delay":0.305
},
{
"type":"net_delay",
"net":
{
"log_name":"A_Sig",
"phy_name":"A_Sig"
},
"arrive":1.859,
"delay":0.407
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":1.859,
"delay":0.000
}
]
}
]]>
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- -------------- ---------------- --------- --------------------- ------
A_Sig_c.ff_inst/CLK->A_Sig_c.ff_inst/Q SLICE REG_DEL 0.305 1.452 2
A_Sig NET DELAY 0.407 1.859 2
A_Sig1.ff_inst/DF ENDPOINT 0.000 1.859 1
Destination Clock Path
<![CDATA[
{
"path_begin":
{
"type":"port",
"log_name":"Clk",
"phy_name":"Clk"
},
"path_end":
{
"type":"pin",
"log_name":"A_Sig1.ff_inst/CLK",
"phy_name":"A_Sig1.ff_inst/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":10.000,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"Clk",
"phy_name":"Clk"
},
"arrive":10.000,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"Clk_pad.bb_inst/B",
"phy_name":"Clk_pad.bb_inst/IOPAD"
},
"pin1":
{
"log_name":"Clk_pad.bb_inst/O",
"phy_name":"Clk_pad.bb_inst/PADDI"
},
"arrive":10.440,
"delay":0.440
},
{
"type":"net_delay",
"net":
{
"log_name":"MyPLL/lscc_pll_inst/Clk_c",
"phy_name":"Clk_c"
},
"arrive":10.740,
"delay":0.300
},
{
"type":"site_delay",
"pin0":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
},
"pin1":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
},
"arrive":10.740,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
},
"pin1":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
},
"arrive":10.740,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"MyPLL/lscc_pll_inst/clk1",
"phy_name":"clk1"
},
"arrive":11.147,
"delay":0.407
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":11.147,
"delay":0.000
}
]
}
]]>
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- -------------- ---------------- --------- --------------------- ------
CONSTRAINT 0.000 10.000 1
Clk top CLOCK LATENCY 0.000 10.000 1
Clk NET DELAY 0.000 10.000 1
Clk_pad.bb_inst/B->Clk_pad.bb_inst/O SEIO18A_CORE PADI_DEL 0.440 10.440 1
MyPLL/lscc_pll_inst/Clk_c NET DELAY 0.300 10.740 1
MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP
PLL_CORE 0.000 10.740 2
MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP (TOTAL_ADJUSTMENTS)
PLL_CORE 0.000 10.740 2
MyPLL/lscc_pll_inst/clk1 NET DELAY 0.407 11.147 2
A_Sig1.ff_inst/CLK CLOCK PIN 0.000 11.147 1
Uncertainty -(0.000) 11.147
Common Path Skew 0.000 11.147
Setup time -(-0.035) 11.182
---------------------------------------- -------------- ---------------- --------- --------------------- ------
Required Time 11.182
Arrival Time -(1.859)
---------------------------------------- -------------- ---------------- --------- --------------------- ------
Path Slack (Passed) 9.323
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
End of Detailed Report for timing paths
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
##########################################################
4 Hold at Speed Grade m Corner at 0 Degrees
4.1 Endpoint slacks
-------------------------------------------------------
Listing 2 End Points | Slack
-------------------------------------------------------
A_Sig1.ff_inst/DF | 0.483 ns
B_sig1.ff_inst/DF | 0.792 ns
-------------------------------------------------------
|
Hold # of endpoints with negative slack: | 0
|
-------------------------------------------------------
4.2 Detailed Report
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
Detail report of critical paths
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Detailed Report for timing paths
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++++Path 1 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : A_Sig_c.ff_inst/Q (SLICE)
Path End : A_Sig1.ff_inst/DF (SLICE)
Source Clock : clk1 (R)
Destination Clock: clk1 (R)
Logic Level : 1
Delay Ratio : 70.2% (route), 29.8% (logic)
Clock Skew : 0.000 ns
Hold Constraint : 0.000 ns
Common Path Skew : 0.000 ns
Path Slack : 0.483 ns (Passed)
Source Clock Path
<![CDATA[
{
"path_begin":
{
"type":"port",
"log_name":"Clk",
"phy_name":"Clk"
},
"path_end":
{
"type":"pin",
"log_name":"A_Sig_c.ff_inst/CLK",
"phy_name":"A_Sig_c.ff_inst/CLK"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"Clk",
"phy_name":"Clk"
},
"arrive":0.000,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"Clk_pad.bb_inst/B",
"phy_name":"Clk_pad.bb_inst/IOPAD"
},
"pin1":
{
"log_name":"Clk_pad.bb_inst/O",
"phy_name":"Clk_pad.bb_inst/PADDI"
},
"arrive":0.366,
"delay":0.366
},
{
"type":"net_delay",
"net":
{
"log_name":"MyPLL/lscc_pll_inst/Clk_c",
"phy_name":"Clk_c"
},
"arrive":0.666,
"delay":0.300
},
{
"type":"site_delay",
"pin0":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
},
"pin1":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
},
"arrive":0.666,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
},
"pin1":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
},
"arrive":0.666,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"MyPLL/lscc_pll_inst/clk1",
"phy_name":"clk1"
},
"arrive":1.073,
"delay":0.407
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":1.073,
"delay":0.000
}
]
}
]]>
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- -------------- ---------------- ----- --------------------- ------
Clk top CLOCK LATENCY 0.000 0.000 1
Clk NET DELAY 0.000 0.000 1
Clk_pad.bb_inst/B->Clk_pad.bb_inst/O SEIO18A_CORE PADI_DEL 0.366 0.366 1
MyPLL/lscc_pll_inst/Clk_c NET DELAY 0.300 0.666 1
MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP
PLL_CORE 0.000 0.666 2
MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP (TOTAL_ADJUSTMENTS)
PLL_CORE 0.000 0.666 2
MyPLL/lscc_pll_inst/clk1 NET DELAY 0.407 1.073 2
A_Sig_c.ff_inst/CLK CLOCK PIN 0.000 1.073 1
Data Path
<![CDATA[
{
"path_begin":
{
"type":"pin",
"log_name":"A_Sig_c.ff_inst/Q",
"phy_name":"A_Sig_c.ff_inst/Q0"
},
"path_end":
{
"type":"pin",
"log_name":"A_Sig1.ff_inst/DF",
"phy_name":"A_Sig1.ff_inst/M0"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"A_Sig_c.ff_inst/CLK",
"phy_name":"A_Sig_c.ff_inst/CLK"
},
"pin1":
{
"log_name":"A_Sig_c.ff_inst/Q",
"phy_name":"A_Sig_c.ff_inst/Q0"
},
"arrive":1.246,
"delay":0.173
},
{
"type":"net_delay",
"net":
{
"log_name":"A_Sig",
"phy_name":"A_Sig"
},
"arrive":1.653,
"delay":0.407
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":1.653,
"delay":0.000
}
]
}
]]>
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- -------------- ---------------- ----- --------------------- ------
A_Sig_c.ff_inst/CLK->A_Sig_c.ff_inst/Q SLICE REG_DEL 0.173 1.246 2
A_Sig NET DELAY 0.407 1.653 2
A_Sig1.ff_inst/DF ENDPOINT 0.000 1.653 1
Destination Clock Path
<![CDATA[
{
"path_begin":
{
"type":"port",
"log_name":"Clk",
"phy_name":"Clk"
},
"path_end":
{
"type":"pin",
"log_name":"A_Sig1.ff_inst/CLK",
"phy_name":"A_Sig1.ff_inst/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":0.000,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"Clk",
"phy_name":"Clk"
},
"arrive":0.000,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"Clk_pad.bb_inst/B",
"phy_name":"Clk_pad.bb_inst/IOPAD"
},
"pin1":
{
"log_name":"Clk_pad.bb_inst/O",
"phy_name":"Clk_pad.bb_inst/PADDI"
},
"arrive":0.366,
"delay":0.366
},
{
"type":"net_delay",
"net":
{
"log_name":"MyPLL/lscc_pll_inst/Clk_c",
"phy_name":"Clk_c"
},
"arrive":0.666,
"delay":0.300
},
{
"type":"site_delay",
"pin0":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
},
"pin1":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
},
"arrive":0.666,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
},
"pin1":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
},
"arrive":0.666,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"MyPLL/lscc_pll_inst/clk1",
"phy_name":"clk1"
},
"arrive":1.073,
"delay":0.407
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":1.073,
"delay":0.000
}
]
}
]]>
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- -------------- ---------------- ----- --------------------- ------
CONSTRAINT 0.000 0.000 1
Clk top CLOCK LATENCY 0.000 0.000 1
Clk NET DELAY 0.000 0.000 1
Clk_pad.bb_inst/B->Clk_pad.bb_inst/O SEIO18A_CORE PADI_DEL 0.366 0.366 1
MyPLL/lscc_pll_inst/Clk_c NET DELAY 0.300 0.666 1
MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP
PLL_CORE 0.000 0.666 2
MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP (TOTAL_ADJUSTMENTS)
PLL_CORE 0.000 0.666 2
MyPLL/lscc_pll_inst/clk1 NET DELAY 0.407 1.073 2
A_Sig1.ff_inst/CLK CLOCK PIN 0.000 1.073 1
Uncertainty 0.000 1.073
Common Path Skew 0.000 1.073
Hold time 0.097 1.170
---------------------------------------- -------------- ---------------- ----- --------------------- ------
Required Time -1.170
Arrival Time 1.653
---------------------------------------- -------------- ---------------- ----- --------------------- ------
Path Slack (Passed) 0.483
++++ Path 2 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : B_sig_c.ff_inst/Q (SLICE)
Path End : B_sig1.ff_inst/DF (SLICE)
Source Clock : clk2 (R)
Destination Clock: clk2 (R)
Logic Level : 2
Delay Ratio : 67.5% (route), 32.5% (logic)
Clock Skew : 0.000 ns
Hold Constraint : 0.000 ns
Common Path Skew : 0.000 ns
Path Slack : 0.792 ns (Passed)
Source Clock Path
<![CDATA[
{
"path_begin":
{
"type":"port",
"log_name":"Clk",
"phy_name":"Clk"
},
"path_end":
{
"type":"pin",
"log_name":"B_sig_c.ff_inst/CLK",
"phy_name":"B_sig_c.ff_inst/CLK"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"Clk",
"phy_name":"Clk"
},
"arrive":0.000,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"Clk_pad.bb_inst/B",
"phy_name":"Clk_pad.bb_inst/IOPAD"
},
"pin1":
{
"log_name":"Clk_pad.bb_inst/O",
"phy_name":"Clk_pad.bb_inst/PADDI"
},
"arrive":0.366,
"delay":0.366
},
{
"type":"net_delay",
"net":
{
"log_name":"MyPLL/lscc_pll_inst/Clk_c",
"phy_name":"Clk_c"
},
"arrive":0.666,
"delay":0.300
},
{
"type":"site_delay",
"pin0":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
},
"pin1":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS"
},
"arrive":0.666,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
},
"pin1":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS"
},
"arrive":0.666,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"MyPLL/lscc_pll_inst/clk2",
"phy_name":"clk2"
},
"arrive":1.073,
"delay":0.407
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":1.073,
"delay":0.000
}
]
}
]]>
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- -------------- ---------------- ----- --------------------- ------
Clk top CLOCK LATENCY 0.000 0.000 1
Clk NET DELAY 0.000 0.000 1
Clk_pad.bb_inst/B->Clk_pad.bb_inst/O SEIO18A_CORE PADI_DEL 0.366 0.366 1
MyPLL/lscc_pll_inst/Clk_c NET DELAY 0.300 0.666 1
MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS
PLL_CORE 0.000 0.666 2
MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS (TOTAL_ADJUSTMENTS)
PLL_CORE 0.000 0.666 2
MyPLL/lscc_pll_inst/clk2 NET DELAY 0.407 1.073 2
B_sig_c.ff_inst/CLK CLOCK PIN 0.000 1.073 1
Data Path
<![CDATA[
{
"path_begin":
{
"type":"pin",
"log_name":"B_sig_c.ff_inst/Q",
"phy_name":"B_sig_c.ff_inst/Q0"
},
"path_end":
{
"type":"pin",
"log_name":"B_sig1.ff_inst/DF",
"phy_name":"B_sig1.ff_inst/M0"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"B_sig_c.ff_inst/CLK",
"phy_name":"B_sig_c.ff_inst/CLK"
},
"pin1":
{
"log_name":"B_sig_c.ff_inst/Q",
"phy_name":"B_sig_c.ff_inst/Q0"
},
"arrive":1.246,
"delay":0.173
},
{
"type":"net_delay",
"net":
{
"log_name":"B_sig",
"phy_name":"B_sig"
},
"arrive":1.546,
"delay":0.300
},
{
"type":"site_delay",
"pin0":
{
"log_name":"i8_2_lut/A",
"phy_name":"i8_2_lut/A0"
},
"pin1":
{
"log_name":"i8_2_lut/Z",
"phy_name":"i8_2_lut/F0"
},
"arrive":1.662,
"delay":0.116
},
{
"type":"net_delay",
"net":
{
"log_name":"out2_c_N_1",
"phy_name":"out2_c_N_1"
},
"arrive":1.962,
"delay":0.300
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":1.962,
"delay":0.000
}
]
}
]]>
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- -------------- ---------------- ----- --------------------- ------
B_sig_c.ff_inst/CLK->B_sig_c.ff_inst/Q SLICE REG_DEL 0.173 1.246 1
B_sig NET DELAY 0.300 1.546 1
i8_2_lut/A->i8_2_lut/Z SLICE CTOF_DEL 0.116 1.662 1
out2_c_N_1 NET DELAY 0.300 1.962 1
B_sig1.ff_inst/DF ENDPOINT 0.000 1.962 1
Destination Clock Path
<![CDATA[
{
"path_begin":
{
"type":"port",
"log_name":"Clk",
"phy_name":"Clk"
},
"path_end":
{
"type":"pin",
"log_name":"B_sig1.ff_inst/CLK",
"phy_name":"B_sig1.ff_inst/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":0.000,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"Clk",
"phy_name":"Clk"
},
"arrive":0.000,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"Clk_pad.bb_inst/B",
"phy_name":"Clk_pad.bb_inst/IOPAD"
},
"pin1":
{
"log_name":"Clk_pad.bb_inst/O",
"phy_name":"Clk_pad.bb_inst/PADDI"
},
"arrive":0.366,
"delay":0.366
},
{
"type":"net_delay",
"net":
{
"log_name":"MyPLL/lscc_pll_inst/Clk_c",
"phy_name":"Clk_c"
},
"arrive":0.666,
"delay":0.300
},
{
"type":"site_delay",
"pin0":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
},
"pin1":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS"
},
"arrive":0.666,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
},
"pin1":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS"
},
"arrive":0.666,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"MyPLL/lscc_pll_inst/clk2",
"phy_name":"clk2"
},
"arrive":1.073,
"delay":0.407
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":1.073,
"delay":0.000
}
]
}
]]>
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- -------------- ---------------- ----- --------------------- ------
CONSTRAINT 0.000 0.000 1
Clk top CLOCK LATENCY 0.000 0.000 1
Clk NET DELAY 0.000 0.000 1
Clk_pad.bb_inst/B->Clk_pad.bb_inst/O SEIO18A_CORE PADI_DEL 0.366 0.366 1
MyPLL/lscc_pll_inst/Clk_c NET DELAY 0.300 0.666 1
MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS
PLL_CORE 0.000 0.666 2
MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS (TOTAL_ADJUSTMENTS)
PLL_CORE 0.000 0.666 2
MyPLL/lscc_pll_inst/clk2 NET DELAY 0.407 1.073 2
B_sig1.ff_inst/CLK CLOCK PIN 0.000 1.073 1
Uncertainty 0.000 1.073
Common Path Skew 0.000 1.073
Hold time 0.097 1.170
---------------------------------------- -------------- ---------------- ----- --------------------- ------
Required Time -1.170
Arrival Time 1.962
---------------------------------------- -------------- ---------------- ----- --------------------- ------
Path Slack (Passed) 0.792
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End of Detailed Report for timing paths
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