Timing Report
Lattice Timing Report - Setup and Hold, Version Radiant Software (64-bit) 2025.1.1.308.0
Wed Nov 12 12:36:06 2025
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2025 Lattice Semiconductor Corporation, All rights reserved.
Command line: timing -sethld -v 10 -u 10 -endpoints 10 -nperend 5 -sp 9_High-Performance_1.0V -hsp m -pwrprd -html -rpt LAB01_impl_1.twr LAB01_impl_1.udb -gui -msgset C:/Users/Mourad Zakhama/Downloads/Lab-Files/Radiant Lab/LAB_01/promote.xml
-------------------------------------------
Design: top
Family: LFCPNX
Device: LFCPNX-50
Package: CBG256
Performance: 9_High-Performance_1.0V
Package Status: Final Version 16
Performance Hardware Data Status : Final Version 7.0
-------------------------------------------
=====================================================================
Table of Contents
=====================================================================
1 Timing Overview
1.1 SDC Constraints
1.2 Constraint Coverage
1.3 Overall Summary
1.4 Unconstrained Report
1.5 Combinational Loop
2 Setup at Speed Grade 9_High-Performance_1.0V Corner at 85 Degrees
2.1 Clock Summary
2.2 Endpoint slacks
2.3 Detailed Report
3 Setup at Speed Grade 9_High-Performance_1.0V Corner at 0 Degrees
3.1 Clock Summary
3.2 Endpoint slacks
3.3 Detailed Report
4 Hold at Speed Grade m Corner at 0 Degrees
4.1 Endpoint slacks
4.2 Detailed Report
=====================================================================
End of Table of Contents
=====================================================================
1 Timing Overview
1.1 SDC Constraints
create_generated_clock -name {clk2} -source [get_pins {MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK}] -multiply_by 2 [get_pins {MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS }]
create_generated_clock -name {clk1} -source [get_pins {MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK}] -multiply_by 2 [get_pins {MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP }]
create_clock -name {Clk} -period 20 [get_ports Clk]
1.2 Constraint Coverage
Constraint Coverage: 45.4545%
1.3 Overall Summary
Setup at Speed Grade 9_High-Performance_1.0V Corner at 85 Degrees Timing Errors: 1 endpoints; Total Negative Slack: 1.986 ns
Setup at Speed Grade 9_High-Performance_1.0V Corner at 0 Degrees Timing Errors: 1 endpoints; Total Negative Slack: 2.002 ns
Hold at Speed Grade m Corner at 0 Degrees Timing Errors: 0 endpoints; Total Negative Slack: 0.000 ns
1.4 Unconstrained Report
1.4.1 Unconstrained Start/End Points
Clocked but unconstrained timing start points
-------------------------------------------------------------------
Listing 2 Start Points | Type
-------------------------------------------------------------------
B_sig1.ff_inst/Q | No required time
A_Sig1.ff_inst/Q | No required time
-------------------------------------------------------------------
|
Number of unconstrained timing start po |
ints | 2
|
-------------------------------------------------------------------
Clocked but unconstrained timing end points
-------------------------------------------------------------------
Listing 2 End Points | Type
-------------------------------------------------------------------
A_Sig_c.ff_inst/DF | No arrival time
B_sig_c.ff_inst/DF | No arrival time
-------------------------------------------------------------------
|
Number of unconstrained timing end poin |
ts | 2
|
-------------------------------------------------------------------
1.4.2 Start/End Points Without Timing Constraints
I/O ports without constraint
----------------------------
Possible constraints to use on I/O ports are:
set_input_delay,
set_output_delay,
set_max_delay,
create_clock,
create_generated_clock,
...
-------------------------------------------------------------------
Listing 4 Start or End Points | Type
-------------------------------------------------------------------
A | input
B | input
out1 | output
out2 | output
-------------------------------------------------------------------
|
Number of I/O ports without constraint | 4
|
-------------------------------------------------------------------
Nets without clock definition
Define a clock on a top level port or a generated clock on a clock divider pin associated with this net(s).
--------------------------------------------------
There is no instance satisfying reporting criteria
1.5 Combinational Loop
None
2 Setup at Speed Grade 9_High-Performance_1.0V Corner at 85 Degrees
2.1 Clock Summary
2.1.1 Clock "clk1"
create_generated_clock -name {clk1} -source [get_pins {MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK}] -multiply_by 2 [get_pins {MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP }]
Single Clock Domain
-------------------------------------------------------------------------------------------------------
Clock clk1 | | Period | Frequency
-------------------------------------------------------------------------------------------------------
From clk1 | Target | 10.000 ns | 100.000 MHz
| Actual (all paths) | 2.796 ns | 357.654 MHz
A_Sig_c.ff_inst/CLK (MPW) | (50% duty cycle) | 2.000 ns | 500.000 MHz
-------------------------------------------------------------------------------------------------------
Clock Domain Crossing
------------------------------------------------------------------------------------------------------
Clock clk1 | Worst Time Between Edges | Comment
------------------------------------------------------------------------------------------------------
From clk2 | ---- | No path
From Clk | ---- | No path
------------------------------------------------------------------------------------------------------
2.1.2 Clock "clk2"
create_generated_clock -name {clk2} -source [get_pins {MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK}] -multiply_by 2 [get_pins {MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS }]
Single Clock Domain
-------------------------------------------------------------------------------------------------------
Clock clk2 | | Period | Frequency
-------------------------------------------------------------------------------------------------------
From clk2 | Target | 10.000 ns | 100.000 MHz
| Actual (all paths) | 2.000 ns | 500.000 MHz
B_sig1.ff_inst/CLK (MPW) | (50% duty cycle) | 2.000 ns | 500.000 MHz
-------------------------------------------------------------------------------------------------------
Clock Domain Crossing
------------------------------------------------------------------------------------------------------
Clock clk2 | Worst Time Between Edges | Comment
------------------------------------------------------------------------------------------------------
From clk1 | 2.500 ns | slack = -1.986 ns
From Clk | ---- | No path
------------------------------------------------------------------------------------------------------
2.1.3 Clock "Clk"
create_clock -name {Clk} -period 20 [get_ports Clk]
Single Clock Domain
-------------------------------------------------------------------------------------------------------
Clock Clk | | Period | Frequency
-------------------------------------------------------------------------------------------------------
From Clk | Target | 20.000 ns | 50.000 MHz
| Actual (all paths) | 5.000 ns | 200.000 MHz
Clk_pad.bb_inst/B (MPW) | (50% duty cycle) | 5.000 ns | 200.000 MHz
-------------------------------------------------------------------------------------------------------
Clock Domain Crossing
------------------------------------------------------------------------------------------------------
Clock Clk | Worst Time Between Edges | Comment
------------------------------------------------------------------------------------------------------
From clk1 | ---- | No path
From clk2 | ---- | No path
------------------------------------------------------------------------------------------------------
2.2 Endpoint slacks
-------------------------------------------------------
Listing 2 End Points | Slack
-------------------------------------------------------
B_sig1.ff_inst/DF | -1.986 ns
A_Sig1.ff_inst/DF | 7.204 ns
-------------------------------------------------------
|
Setup # of endpoints with negative slack:| 1
|
-------------------------------------------------------
2.3 Detailed Report
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
Detail report of critical paths
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Detailed Report for timing paths
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++++Path 1 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : A_Sig_c.ff_inst/Q (SLICE_R4C4D)
Path End : B_sig1.ff_inst/DF (SLICE_R50C100D)
Source Clock : clk1 (R)
Destination Clock: clk2 (R)
Logic Level : 2
Delay Ratio : 88.5% (route), 11.5% (logic)
Clock Skew : -0.163 ns
Setup Constraint : 2.500 ns
Common Path Skew : 0.017 ns
Path Slack : -1.986 ns (Failed)
Source Clock Path
<![CDATA[
{
"path_begin":
{
"type":"port",
"log_name":"Clk",
"phy_name":"Clk"
},
"path_end":
{
"type":"pin",
"log_name":"A_Sig_c.ff_inst/CLK",
"phy_name":"A_Sig_c.ff_inst/CLK"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"Clk",
"phy_name":"Clk"
},
"arrive":0.000,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"Clk_pad.bb_inst/B",
"phy_name":"Clk_pad.bb_inst/IOPAD"
},
"pin1":
{
"log_name":"Clk_pad.bb_inst/O",
"phy_name":"Clk_pad.bb_inst/PADDI"
},
"arrive":0.464,
"delay":0.464
},
{
"type":"net_delay",
"net":
{
"log_name":"MyPLL/lscc_pll_inst/Clk_c",
"phy_name":"Clk_c"
},
"arrive":0.773,
"delay":0.309
},
{
"type":"site_delay",
"pin0":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
},
"pin1":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
},
"arrive":0.773,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
},
"pin1":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
},
"arrive":0.773,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"MyPLL/lscc_pll_inst/clk1",
"phy_name":"clk1"
},
"arrive":3.272,
"delay":2.499
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":3.272,
"delay":0.000
}
]
}
]]>
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ---------------- ---------------- --------- --------------------- ------
Clk top CLOCK LATENCY 0.000 0.000 1
Clk NET DELAY 0.000 0.000 1
Clk_pad.bb_inst/B->Clk_pad.bb_inst/O SEIO18A_CORE_K15 PADI_DEL 0.464 0.464 1
MyPLL/lscc_pll_inst/Clk_c NET DELAY 0.309 0.773 1
MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP
PLL_CORE_PLL_LLC 0.000 0.773 2
MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP (TOTAL_ADJUSTMENTS)
PLL_CORE_PLL_LLC 0.000 0.773 2
MyPLL/lscc_pll_inst/clk1 NET DELAY 2.499 3.272 2
A_Sig_c.ff_inst/CLK CLOCK PIN 0.000 3.272 1
Data Path
<![CDATA[
{
"path_begin":
{
"type":"pin",
"log_name":"A_Sig_c.ff_inst/Q",
"phy_name":"A_Sig_c.ff_inst/Q0"
},
"path_end":
{
"type":"pin",
"log_name":"B_sig1.ff_inst/DF",
"phy_name":"B_sig1.ff_inst/M0"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"A_Sig_c.ff_inst/CLK",
"phy_name":"A_Sig_c.ff_inst/CLK"
},
"pin1":
{
"log_name":"A_Sig_c.ff_inst/Q",
"phy_name":"A_Sig_c.ff_inst/Q0"
},
"arrive":3.564,
"delay":0.292
},
{
"type":"net_delay",
"net":
{
"log_name":"A_Sig",
"phy_name":"A_Sig"
},
"arrive":7.318,
"delay":3.754
},
{
"type":"site_delay",
"pin0":
{
"log_name":"i8_2_lut/B",
"phy_name":"i8_2_lut/D0"
},
"pin1":
{
"log_name":"i8_2_lut/Z",
"phy_name":"i8_2_lut/F0"
},
"arrive":7.531,
"delay":0.213
},
{
"type":"net_delay",
"net":
{
"log_name":"out2_c_N_1",
"phy_name":"out2_c_N_1"
},
"arrive":7.647,
"delay":0.116
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":7.647,
"delay":0.000
}
]
}
]]>
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ---------------- ---------------- --------- --------------------- ------
A_Sig_c.ff_inst/CLK->A_Sig_c.ff_inst/Q SLICE_R4C4D REG_DEL 0.292 3.564 2
A_Sig NET DELAY 3.754 7.318 2
i8_2_lut/B->i8_2_lut/Z SLICE_R50C100B CTOF_DEL 0.213 7.531 1
out2_c_N_1 NET DELAY 0.116 7.647 1
B_sig1.ff_inst/DF ENDPOINT 0.000 7.647 1
Destination Clock Path
<![CDATA[
{
"path_begin":
{
"type":"port",
"log_name":"Clk",
"phy_name":"Clk"
},
"path_end":
{
"type":"pin",
"log_name":"B_sig1.ff_inst/CLK",
"phy_name":"B_sig1.ff_inst/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":2.500,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"Clk",
"phy_name":"Clk"
},
"arrive":2.500,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"Clk_pad.bb_inst/B",
"phy_name":"Clk_pad.bb_inst/IOPAD"
},
"pin1":
{
"log_name":"Clk_pad.bb_inst/O",
"phy_name":"Clk_pad.bb_inst/PADDI"
},
"arrive":2.964,
"delay":0.464
},
{
"type":"net_delay",
"net":
{
"log_name":"MyPLL/lscc_pll_inst/Clk_c",
"phy_name":"Clk_c"
},
"arrive":3.254,
"delay":0.290
},
{
"type":"site_delay",
"pin0":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
},
"pin1":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS"
},
"arrive":3.254,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
},
"pin1":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS"
},
"arrive":3.254,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"MyPLL/lscc_pll_inst/clk2",
"phy_name":"clk2"
},
"arrive":5.609,
"delay":2.355
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":5.609,
"delay":0.000
}
]
}
]]>
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ---------------- ---------------- --------- --------------------- ------
CONSTRAINT 0.000 2.500 1
Clk top CLOCK LATENCY 0.000 2.500 1
Clk NET DELAY 0.000 2.500 1
Clk_pad.bb_inst/B->Clk_pad.bb_inst/O SEIO18A_CORE_K15 PADI_DEL 0.464 2.964 1
MyPLL/lscc_pll_inst/Clk_c NET DELAY 0.290 3.254 1
MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS
PLL_CORE_PLL_LLC 0.000 3.254 2
MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS (TOTAL_ADJUSTMENTS)
PLL_CORE_PLL_LLC 0.000 3.254 2
MyPLL/lscc_pll_inst/clk2 NET DELAY 2.355 5.609 2
B_sig1.ff_inst/CLK CLOCK PIN 0.000 5.609 1
Uncertainty -(0.000) 5.609
Common Path Skew 0.017 5.626
Setup time -(-0.035) 5.661
---------------------------------------- ---------------- ---------------- --------- --------------------- ------
Required Time 5.661
Arrival Time -(7.647)
---------------------------------------- ---------------- ---------------- --------- --------------------- ------
Path Slack (Failed) -1.986
++++ Path 2 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : A_Sig_c.ff_inst/Q (SLICE_R4C4D)
Path End : A_Sig1.ff_inst/DF (SLICE_R2C100D)
Source Clock : clk1 (R)
Destination Clock: clk1 (R)
Logic Level : 1
Delay Ratio : 89.3% (route), 10.7% (logic)
Clock Skew : -0.163 ns
Setup Constraint : 10.000 ns
Common Path Skew : 0.057 ns
Path Slack : 7.204 ns (Passed)
Source Clock Path
<![CDATA[
{
"path_begin":
{
"type":"port",
"log_name":"Clk",
"phy_name":"Clk"
},
"path_end":
{
"type":"pin",
"log_name":"A_Sig_c.ff_inst/CLK",
"phy_name":"A_Sig_c.ff_inst/CLK"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"Clk",
"phy_name":"Clk"
},
"arrive":0.000,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"Clk_pad.bb_inst/B",
"phy_name":"Clk_pad.bb_inst/IOPAD"
},
"pin1":
{
"log_name":"Clk_pad.bb_inst/O",
"phy_name":"Clk_pad.bb_inst/PADDI"
},
"arrive":0.464,
"delay":0.464
},
{
"type":"net_delay",
"net":
{
"log_name":"MyPLL/lscc_pll_inst/Clk_c",
"phy_name":"Clk_c"
},
"arrive":0.773,
"delay":0.309
},
{
"type":"site_delay",
"pin0":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
},
"pin1":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
},
"arrive":0.773,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
},
"pin1":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
},
"arrive":0.773,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"MyPLL/lscc_pll_inst/clk1",
"phy_name":"clk1"
},
"arrive":3.272,
"delay":2.499
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":3.272,
"delay":0.000
}
]
}
]]>
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ---------------- ---------------- --------- --------------------- ------
Clk top CLOCK LATENCY 0.000 0.000 1
Clk NET DELAY 0.000 0.000 1
Clk_pad.bb_inst/B->Clk_pad.bb_inst/O SEIO18A_CORE_K15 PADI_DEL 0.464 0.464 1
MyPLL/lscc_pll_inst/Clk_c NET DELAY 0.309 0.773 1
MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP
PLL_CORE_PLL_LLC 0.000 0.773 2
MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP (TOTAL_ADJUSTMENTS)
PLL_CORE_PLL_LLC 0.000 0.773 2
MyPLL/lscc_pll_inst/clk1 NET DELAY 2.499 3.272 2
A_Sig_c.ff_inst/CLK CLOCK PIN 0.000 3.272 1
Data Path
<![CDATA[
{
"path_begin":
{
"type":"pin",
"log_name":"A_Sig_c.ff_inst/Q",
"phy_name":"A_Sig_c.ff_inst/Q0"
},
"path_end":
{
"type":"pin",
"log_name":"A_Sig1.ff_inst/DF",
"phy_name":"A_Sig1.ff_inst/M0"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"A_Sig_c.ff_inst/CLK",
"phy_name":"A_Sig_c.ff_inst/CLK"
},
"pin1":
{
"log_name":"A_Sig_c.ff_inst/Q",
"phy_name":"A_Sig_c.ff_inst/Q0"
},
"arrive":3.564,
"delay":0.292
},
{
"type":"net_delay",
"net":
{
"log_name":"A_Sig",
"phy_name":"A_Sig"
},
"arrive":5.995,
"delay":2.431
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":5.995,
"delay":0.000
}
]
}
]]>
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ---------------- ---------------- --------- --------------------- ------
A_Sig_c.ff_inst/CLK->A_Sig_c.ff_inst/Q SLICE_R4C4D REG_DEL 0.292 3.564 2
A_Sig NET DELAY 2.431 5.995 2
A_Sig1.ff_inst/DF ENDPOINT 0.000 5.995 1
Destination Clock Path
<![CDATA[
{
"path_begin":
{
"type":"port",
"log_name":"Clk",
"phy_name":"Clk"
},
"path_end":
{
"type":"pin",
"log_name":"A_Sig1.ff_inst/CLK",
"phy_name":"A_Sig1.ff_inst/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":10.000,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"Clk",
"phy_name":"Clk"
},
"arrive":10.000,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"Clk_pad.bb_inst/B",
"phy_name":"Clk_pad.bb_inst/IOPAD"
},
"pin1":
{
"log_name":"Clk_pad.bb_inst/O",
"phy_name":"Clk_pad.bb_inst/PADDI"
},
"arrive":10.464,
"delay":0.464
},
{
"type":"net_delay",
"net":
{
"log_name":"MyPLL/lscc_pll_inst/Clk_c",
"phy_name":"Clk_c"
},
"arrive":10.754,
"delay":0.290
},
{
"type":"site_delay",
"pin0":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
},
"pin1":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
},
"arrive":10.754,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
},
"pin1":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
},
"arrive":10.754,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"MyPLL/lscc_pll_inst/clk1",
"phy_name":"clk1"
},
"arrive":13.109,
"delay":2.355
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":13.109,
"delay":0.000
}
]
}
]]>
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ---------------- ---------------- --------- --------------------- ------
CONSTRAINT 0.000 10.000 1
Clk top CLOCK LATENCY 0.000 10.000 1
Clk NET DELAY 0.000 10.000 1
Clk_pad.bb_inst/B->Clk_pad.bb_inst/O SEIO18A_CORE_K15 PADI_DEL 0.464 10.464 1
MyPLL/lscc_pll_inst/Clk_c NET DELAY 0.290 10.754 1
MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP
PLL_CORE_PLL_LLC 0.000 10.754 2
MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP (TOTAL_ADJUSTMENTS)
PLL_CORE_PLL_LLC 0.000 10.754 2
MyPLL/lscc_pll_inst/clk1 NET DELAY 2.355 13.109 2
A_Sig1.ff_inst/CLK CLOCK PIN 0.000 13.109 1
Uncertainty -(0.000) 13.109
Common Path Skew 0.057 13.166
Setup time -(-0.033) 13.199
---------------------------------------- ---------------- ---------------- --------- --------------------- ------
Required Time 13.199
Arrival Time -(5.995)
---------------------------------------- ---------------- ---------------- --------- --------------------- ------
Path Slack (Passed) 7.204
++++ Path 3 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : B_sig_c.ff_inst/Q (SLICE_R50C100C)
Path End : B_sig1.ff_inst/DF (SLICE_R50C100D)
Source Clock : clk2 (R)
Destination Clock: clk2 (R)
Logic Level : 2
Delay Ratio : 40.4% (route), 59.6% (logic)
Clock Skew : -0.163 ns
Setup Constraint : 10.000 ns
Common Path Skew : 0.161 ns
Path Slack : 9.166 ns (Passed)
Source Clock Path
<![CDATA[
{
"path_begin":
{
"type":"port",
"log_name":"Clk",
"phy_name":"Clk"
},
"path_end":
{
"type":"pin",
"log_name":"B_sig_c.ff_inst/CLK",
"phy_name":"B_sig_c.ff_inst/CLK"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"Clk",
"phy_name":"Clk"
},
"arrive":0.000,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"Clk_pad.bb_inst/B",
"phy_name":"Clk_pad.bb_inst/IOPAD"
},
"pin1":
{
"log_name":"Clk_pad.bb_inst/O",
"phy_name":"Clk_pad.bb_inst/PADDI"
},
"arrive":0.464,
"delay":0.464
},
{
"type":"net_delay",
"net":
{
"log_name":"MyPLL/lscc_pll_inst/Clk_c",
"phy_name":"Clk_c"
},
"arrive":0.773,
"delay":0.309
},
{
"type":"site_delay",
"pin0":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
},
"pin1":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS"
},
"arrive":0.773,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
},
"pin1":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS"
},
"arrive":0.773,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"MyPLL/lscc_pll_inst/clk2",
"phy_name":"clk2"
},
"arrive":3.272,
"delay":2.499
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":3.272,
"delay":0.000
}
]
}
]]>
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ---------------- ---------------- --------- --------------------- ------
Clk top CLOCK LATENCY 0.000 0.000 1
Clk NET DELAY 0.000 0.000 1
Clk_pad.bb_inst/B->Clk_pad.bb_inst/O SEIO18A_CORE_K15 PADI_DEL 0.464 0.464 1
MyPLL/lscc_pll_inst/Clk_c NET DELAY 0.309 0.773 1
MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS
PLL_CORE_PLL_LLC 0.000 0.773 2
MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS (TOTAL_ADJUSTMENTS)
PLL_CORE_PLL_LLC 0.000 0.773 2
MyPLL/lscc_pll_inst/clk2 NET DELAY 2.499 3.272 2
B_sig_c.ff_inst/CLK CLOCK PIN 0.000 3.272 1
Data Path
<![CDATA[
{
"path_begin":
{
"type":"pin",
"log_name":"B_sig_c.ff_inst/Q",
"phy_name":"B_sig_c.ff_inst/Q0"
},
"path_end":
{
"type":"pin",
"log_name":"B_sig1.ff_inst/DF",
"phy_name":"B_sig1.ff_inst/M0"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"B_sig_c.ff_inst/CLK",
"phy_name":"B_sig_c.ff_inst/CLK"
},
"pin1":
{
"log_name":"B_sig_c.ff_inst/Q",
"phy_name":"B_sig_c.ff_inst/Q0"
},
"arrive":3.576,
"delay":0.304
},
{
"type":"net_delay",
"net":
{
"log_name":"B_sig",
"phy_name":"B_sig"
},
"arrive":3.810,
"delay":0.234
},
{
"type":"site_delay",
"pin0":
{
"log_name":"i8_2_lut/A",
"phy_name":"i8_2_lut/B0"
},
"pin1":
{
"log_name":"i8_2_lut/Z",
"phy_name":"i8_2_lut/F0"
},
"arrive":4.023,
"delay":0.213
},
{
"type":"net_delay",
"net":
{
"log_name":"out2_c_N_1",
"phy_name":"out2_c_N_1"
},
"arrive":4.139,
"delay":0.116
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":4.139,
"delay":0.000
}
]
}
]]>
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ---------------- ---------------- --------- --------------------- ------
B_sig_c.ff_inst/CLK->B_sig_c.ff_inst/Q SLICE_R50C100C REG_DEL 0.304 3.576 1
B_sig NET DELAY 0.234 3.810 1
i8_2_lut/A->i8_2_lut/Z SLICE_R50C100B CTOF_DEL 0.213 4.023 1
out2_c_N_1 NET DELAY 0.116 4.139 1
B_sig1.ff_inst/DF ENDPOINT 0.000 4.139 1
Destination Clock Path
<![CDATA[
{
"path_begin":
{
"type":"port",
"log_name":"Clk",
"phy_name":"Clk"
},
"path_end":
{
"type":"pin",
"log_name":"B_sig1.ff_inst/CLK",
"phy_name":"B_sig1.ff_inst/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":10.000,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"Clk",
"phy_name":"Clk"
},
"arrive":10.000,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"Clk_pad.bb_inst/B",
"phy_name":"Clk_pad.bb_inst/IOPAD"
},
"pin1":
{
"log_name":"Clk_pad.bb_inst/O",
"phy_name":"Clk_pad.bb_inst/PADDI"
},
"arrive":10.464,
"delay":0.464
},
{
"type":"net_delay",
"net":
{
"log_name":"MyPLL/lscc_pll_inst/Clk_c",
"phy_name":"Clk_c"
},
"arrive":10.754,
"delay":0.290
},
{
"type":"site_delay",
"pin0":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
},
"pin1":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS"
},
"arrive":10.754,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
},
"pin1":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS"
},
"arrive":10.754,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"MyPLL/lscc_pll_inst/clk2",
"phy_name":"clk2"
},
"arrive":13.109,
"delay":2.355
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":13.109,
"delay":0.000
}
]
}
]]>
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ---------------- ---------------- --------- --------------------- ------
CONSTRAINT 0.000 10.000 1
Clk top CLOCK LATENCY 0.000 10.000 1
Clk NET DELAY 0.000 10.000 1
Clk_pad.bb_inst/B->Clk_pad.bb_inst/O SEIO18A_CORE_K15 PADI_DEL 0.464 10.464 1
MyPLL/lscc_pll_inst/Clk_c NET DELAY 0.290 10.754 1
MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS
PLL_CORE_PLL_LLC 0.000 10.754 2
MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS (TOTAL_ADJUSTMENTS)
PLL_CORE_PLL_LLC 0.000 10.754 2
MyPLL/lscc_pll_inst/clk2 NET DELAY 2.355 13.109 2
B_sig1.ff_inst/CLK CLOCK PIN 0.000 13.109 1
Uncertainty -(0.000) 13.109
Common Path Skew 0.161 13.270
Setup time -(-0.035) 13.305
---------------------------------------- ---------------- ---------------- --------- --------------------- ------
Required Time 13.305
Arrival Time -(4.139)
---------------------------------------- ---------------- ---------------- --------- --------------------- ------
Path Slack (Passed) 9.166
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
End of Detailed Report for timing paths
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
##########################################################
3 Setup at Speed Grade 9_High-Performance_1.0V Corner at 0 Degrees
3.1 Clock Summary
3.1.1 Clock "clk1"
create_generated_clock -name {clk1} -source [get_pins {MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK}] -multiply_by 2 [get_pins {MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP }]
Single Clock Domain
-------------------------------------------------------------------------------------------------------
Clock clk1 | | Period | Frequency
-------------------------------------------------------------------------------------------------------
From clk1 | Target | 10.000 ns | 100.000 MHz
| Actual (all paths) | 2.811 ns | 355.745 MHz
A_Sig_c.ff_inst/CLK (MPW) | (50% duty cycle) | 2.000 ns | 500.000 MHz
-------------------------------------------------------------------------------------------------------
Clock Domain Crossing
------------------------------------------------------------------------------------------------------
Clock clk1 | Worst Time Between Edges | Comment
------------------------------------------------------------------------------------------------------
From clk2 | ---- | No path
From Clk | ---- | No path
------------------------------------------------------------------------------------------------------
3.1.2 Clock "clk2"
create_generated_clock -name {clk2} -source [get_pins {MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK}] -multiply_by 2 [get_pins {MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS }]
Single Clock Domain
-------------------------------------------------------------------------------------------------------
Clock clk2 | | Period | Frequency
-------------------------------------------------------------------------------------------------------
From clk2 | Target | 10.000 ns | 100.000 MHz
| Actual (all paths) | 2.000 ns | 500.000 MHz
B_sig1.ff_inst/CLK (MPW) | (50% duty cycle) | 2.000 ns | 500.000 MHz
-------------------------------------------------------------------------------------------------------
Clock Domain Crossing
------------------------------------------------------------------------------------------------------
Clock clk2 | Worst Time Between Edges | Comment
------------------------------------------------------------------------------------------------------
From clk1 | 2.500 ns | slack = -2.002 ns
From Clk | ---- | No path
------------------------------------------------------------------------------------------------------
3.1.3 Clock "Clk"
create_clock -name {Clk} -period 20 [get_ports Clk]
Single Clock Domain
-------------------------------------------------------------------------------------------------------
Clock Clk | | Period | Frequency
-------------------------------------------------------------------------------------------------------
From Clk | Target | 20.000 ns | 50.000 MHz
| Actual (all paths) | 5.000 ns | 200.000 MHz
Clk_pad.bb_inst/B (MPW) | (50% duty cycle) | 5.000 ns | 200.000 MHz
-------------------------------------------------------------------------------------------------------
Clock Domain Crossing
------------------------------------------------------------------------------------------------------
Clock Clk | Worst Time Between Edges | Comment
------------------------------------------------------------------------------------------------------
From clk1 | ---- | No path
From clk2 | ---- | No path
------------------------------------------------------------------------------------------------------
3.2 Endpoint slacks
-------------------------------------------------------
Listing 2 End Points | Slack
-------------------------------------------------------
B_sig1.ff_inst/DF | -2.002 ns
A_Sig1.ff_inst/DF | 7.189 ns
-------------------------------------------------------
|
Setup # of endpoints with negative slack:| 1
|
-------------------------------------------------------
3.3 Detailed Report
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
Detail report of critical paths
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Detailed Report for timing paths
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++++Path 1 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : A_Sig_c.ff_inst/Q (SLICE_R4C4D)
Path End : B_sig1.ff_inst/DF (SLICE_R50C100D)
Source Clock : clk1 (R)
Destination Clock: clk2 (R)
Logic Level : 2
Delay Ratio : 88.5% (route), 11.5% (logic)
Clock Skew : -0.175 ns
Setup Constraint : 2.500 ns
Common Path Skew : 0.019 ns
Path Slack : -2.002 ns (Failed)
Source Clock Path
<![CDATA[
{
"path_begin":
{
"type":"port",
"log_name":"Clk",
"phy_name":"Clk"
},
"path_end":
{
"type":"pin",
"log_name":"A_Sig_c.ff_inst/CLK",
"phy_name":"A_Sig_c.ff_inst/CLK"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"Clk",
"phy_name":"Clk"
},
"arrive":0.000,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"Clk_pad.bb_inst/B",
"phy_name":"Clk_pad.bb_inst/IOPAD"
},
"pin1":
{
"log_name":"Clk_pad.bb_inst/O",
"phy_name":"Clk_pad.bb_inst/PADDI"
},
"arrive":0.440,
"delay":0.440
},
{
"type":"net_delay",
"net":
{
"log_name":"MyPLL/lscc_pll_inst/Clk_c",
"phy_name":"Clk_c"
},
"arrive":0.766,
"delay":0.326
},
{
"type":"site_delay",
"pin0":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
},
"pin1":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
},
"arrive":0.766,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
},
"pin1":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
},
"arrive":0.766,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"MyPLL/lscc_pll_inst/clk1",
"phy_name":"clk1"
},
"arrive":3.452,
"delay":2.686
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":3.452,
"delay":0.000
}
]
}
]]>
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ---------------- ---------------- --------- --------------------- ------
Clk top CLOCK LATENCY 0.000 0.000 1
Clk NET DELAY 0.000 0.000 1
Clk_pad.bb_inst/B->Clk_pad.bb_inst/O SEIO18A_CORE_K15 PADI_DEL 0.440 0.440 1
MyPLL/lscc_pll_inst/Clk_c NET DELAY 0.326 0.766 1
MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP
PLL_CORE_PLL_LLC 0.000 0.766 2
MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP (TOTAL_ADJUSTMENTS)
PLL_CORE_PLL_LLC 0.000 0.766 2
MyPLL/lscc_pll_inst/clk1 NET DELAY 2.686 3.452 2
A_Sig_c.ff_inst/CLK CLOCK PIN 0.000 3.452 1
Data Path
<![CDATA[
{
"path_begin":
{
"type":"pin",
"log_name":"A_Sig_c.ff_inst/Q",
"phy_name":"A_Sig_c.ff_inst/Q0"
},
"path_end":
{
"type":"pin",
"log_name":"B_sig1.ff_inst/DF",
"phy_name":"B_sig1.ff_inst/M0"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"A_Sig_c.ff_inst/CLK",
"phy_name":"A_Sig_c.ff_inst/CLK"
},
"pin1":
{
"log_name":"A_Sig_c.ff_inst/Q",
"phy_name":"A_Sig_c.ff_inst/Q0"
},
"arrive":3.745,
"delay":0.293
},
{
"type":"net_delay",
"net":
{
"log_name":"A_Sig",
"phy_name":"A_Sig"
},
"arrive":7.510,
"delay":3.765
},
{
"type":"site_delay",
"pin0":
{
"log_name":"i8_2_lut/B",
"phy_name":"i8_2_lut/D0"
},
"pin1":
{
"log_name":"i8_2_lut/Z",
"phy_name":"i8_2_lut/F0"
},
"arrive":7.723,
"delay":0.213
},
{
"type":"net_delay",
"net":
{
"log_name":"out2_c_N_1",
"phy_name":"out2_c_N_1"
},
"arrive":7.833,
"delay":0.110
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":7.833,
"delay":0.000
}
]
}
]]>
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ---------------- ---------------- --------- --------------------- ------
A_Sig_c.ff_inst/CLK->A_Sig_c.ff_inst/Q SLICE_R4C4D REG_DEL 0.293 3.745 2
A_Sig NET DELAY 3.765 7.510 2
i8_2_lut/B->i8_2_lut/Z SLICE_R50C100B CTOF_DEL 0.213 7.723 1
out2_c_N_1 NET DELAY 0.110 7.833 1
B_sig1.ff_inst/DF ENDPOINT 0.000 7.833 1
Destination Clock Path
<![CDATA[
{
"path_begin":
{
"type":"port",
"log_name":"Clk",
"phy_name":"Clk"
},
"path_end":
{
"type":"pin",
"log_name":"B_sig1.ff_inst/CLK",
"phy_name":"B_sig1.ff_inst/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":2.500,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"Clk",
"phy_name":"Clk"
},
"arrive":2.500,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"Clk_pad.bb_inst/B",
"phy_name":"Clk_pad.bb_inst/IOPAD"
},
"pin1":
{
"log_name":"Clk_pad.bb_inst/O",
"phy_name":"Clk_pad.bb_inst/PADDI"
},
"arrive":2.940,
"delay":0.440
},
{
"type":"net_delay",
"net":
{
"log_name":"MyPLL/lscc_pll_inst/Clk_c",
"phy_name":"Clk_c"
},
"arrive":3.246,
"delay":0.306
},
{
"type":"site_delay",
"pin0":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
},
"pin1":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS"
},
"arrive":3.246,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
},
"pin1":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS"
},
"arrive":3.246,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"MyPLL/lscc_pll_inst/clk2",
"phy_name":"clk2"
},
"arrive":5.777,
"delay":2.531
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":5.777,
"delay":0.000
}
]
}
]]>
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ---------------- ---------------- --------- --------------------- ------
CONSTRAINT 0.000 2.500 1
Clk top CLOCK LATENCY 0.000 2.500 1
Clk NET DELAY 0.000 2.500 1
Clk_pad.bb_inst/B->Clk_pad.bb_inst/O SEIO18A_CORE_K15 PADI_DEL 0.440 2.940 1
MyPLL/lscc_pll_inst/Clk_c NET DELAY 0.306 3.246 1
MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS
PLL_CORE_PLL_LLC 0.000 3.246 2
MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS (TOTAL_ADJUSTMENTS)
PLL_CORE_PLL_LLC 0.000 3.246 2
MyPLL/lscc_pll_inst/clk2 NET DELAY 2.531 5.777 2
B_sig1.ff_inst/CLK CLOCK PIN 0.000 5.777 1
Uncertainty -(0.000) 5.777
Common Path Skew 0.019 5.796
Setup time -(-0.035) 5.831
---------------------------------------- ---------------- ---------------- --------- --------------------- ------
Required Time 5.831
Arrival Time -(7.833)
---------------------------------------- ---------------- ---------------- --------- --------------------- ------
Path Slack (Failed) -2.002
++++ Path 2 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : A_Sig_c.ff_inst/Q (SLICE_R4C4D)
Path End : A_Sig1.ff_inst/DF (SLICE_R2C100D)
Source Clock : clk1 (R)
Destination Clock: clk1 (R)
Logic Level : 1
Delay Ratio : 89.3% (route), 10.7% (logic)
Clock Skew : -0.175 ns
Setup Constraint : 10.000 ns
Common Path Skew : 0.062 ns
Path Slack : 7.189 ns (Passed)
Source Clock Path
<![CDATA[
{
"path_begin":
{
"type":"port",
"log_name":"Clk",
"phy_name":"Clk"
},
"path_end":
{
"type":"pin",
"log_name":"A_Sig_c.ff_inst/CLK",
"phy_name":"A_Sig_c.ff_inst/CLK"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"Clk",
"phy_name":"Clk"
},
"arrive":0.000,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"Clk_pad.bb_inst/B",
"phy_name":"Clk_pad.bb_inst/IOPAD"
},
"pin1":
{
"log_name":"Clk_pad.bb_inst/O",
"phy_name":"Clk_pad.bb_inst/PADDI"
},
"arrive":0.440,
"delay":0.440
},
{
"type":"net_delay",
"net":
{
"log_name":"MyPLL/lscc_pll_inst/Clk_c",
"phy_name":"Clk_c"
},
"arrive":0.766,
"delay":0.326
},
{
"type":"site_delay",
"pin0":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
},
"pin1":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
},
"arrive":0.766,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
},
"pin1":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
},
"arrive":0.766,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"MyPLL/lscc_pll_inst/clk1",
"phy_name":"clk1"
},
"arrive":3.452,
"delay":2.686
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":3.452,
"delay":0.000
}
]
}
]]>
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ---------------- ---------------- --------- --------------------- ------
Clk top CLOCK LATENCY 0.000 0.000 1
Clk NET DELAY 0.000 0.000 1
Clk_pad.bb_inst/B->Clk_pad.bb_inst/O SEIO18A_CORE_K15 PADI_DEL 0.440 0.440 1
MyPLL/lscc_pll_inst/Clk_c NET DELAY 0.326 0.766 1
MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP
PLL_CORE_PLL_LLC 0.000 0.766 2
MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP (TOTAL_ADJUSTMENTS)
PLL_CORE_PLL_LLC 0.000 0.766 2
MyPLL/lscc_pll_inst/clk1 NET DELAY 2.686 3.452 2
A_Sig_c.ff_inst/CLK CLOCK PIN 0.000 3.452 1
Data Path
<![CDATA[
{
"path_begin":
{
"type":"pin",
"log_name":"A_Sig_c.ff_inst/Q",
"phy_name":"A_Sig_c.ff_inst/Q0"
},
"path_end":
{
"type":"pin",
"log_name":"A_Sig1.ff_inst/DF",
"phy_name":"A_Sig1.ff_inst/M0"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"A_Sig_c.ff_inst/CLK",
"phy_name":"A_Sig_c.ff_inst/CLK"
},
"pin1":
{
"log_name":"A_Sig_c.ff_inst/Q",
"phy_name":"A_Sig_c.ff_inst/Q0"
},
"arrive":3.745,
"delay":0.293
},
{
"type":"net_delay",
"net":
{
"log_name":"A_Sig",
"phy_name":"A_Sig"
},
"arrive":6.183,
"delay":2.438
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":6.183,
"delay":0.000
}
]
}
]]>
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ---------------- ---------------- --------- --------------------- ------
A_Sig_c.ff_inst/CLK->A_Sig_c.ff_inst/Q SLICE_R4C4D REG_DEL 0.293 3.745 2
A_Sig NET DELAY 2.438 6.183 2
A_Sig1.ff_inst/DF ENDPOINT 0.000 6.183 1
Destination Clock Path
<![CDATA[
{
"path_begin":
{
"type":"port",
"log_name":"Clk",
"phy_name":"Clk"
},
"path_end":
{
"type":"pin",
"log_name":"A_Sig1.ff_inst/CLK",
"phy_name":"A_Sig1.ff_inst/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":10.000,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"Clk",
"phy_name":"Clk"
},
"arrive":10.000,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"Clk_pad.bb_inst/B",
"phy_name":"Clk_pad.bb_inst/IOPAD"
},
"pin1":
{
"log_name":"Clk_pad.bb_inst/O",
"phy_name":"Clk_pad.bb_inst/PADDI"
},
"arrive":10.440,
"delay":0.440
},
{
"type":"net_delay",
"net":
{
"log_name":"MyPLL/lscc_pll_inst/Clk_c",
"phy_name":"Clk_c"
},
"arrive":10.746,
"delay":0.306
},
{
"type":"site_delay",
"pin0":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
},
"pin1":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
},
"arrive":10.746,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
},
"pin1":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
},
"arrive":10.746,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"MyPLL/lscc_pll_inst/clk1",
"phy_name":"clk1"
},
"arrive":13.277,
"delay":2.531
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":13.277,
"delay":0.000
}
]
}
]]>
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ---------------- ---------------- --------- --------------------- ------
CONSTRAINT 0.000 10.000 1
Clk top CLOCK LATENCY 0.000 10.000 1
Clk NET DELAY 0.000 10.000 1
Clk_pad.bb_inst/B->Clk_pad.bb_inst/O SEIO18A_CORE_K15 PADI_DEL 0.440 10.440 1
MyPLL/lscc_pll_inst/Clk_c NET DELAY 0.306 10.746 1
MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP
PLL_CORE_PLL_LLC 0.000 10.746 2
MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP (TOTAL_ADJUSTMENTS)
PLL_CORE_PLL_LLC 0.000 10.746 2
MyPLL/lscc_pll_inst/clk1 NET DELAY 2.531 13.277 2
A_Sig1.ff_inst/CLK CLOCK PIN 0.000 13.277 1
Uncertainty -(0.000) 13.277
Common Path Skew 0.062 13.339
Setup time -(-0.033) 13.372
---------------------------------------- ---------------- ---------------- --------- --------------------- ------
Required Time 13.372
Arrival Time -(6.183)
---------------------------------------- ---------------- ---------------- --------- --------------------- ------
Path Slack (Passed) 7.189
++++ Path 3 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : B_sig_c.ff_inst/Q (SLICE_R50C100C)
Path End : B_sig1.ff_inst/DF (SLICE_R50C100D)
Source Clock : clk2 (R)
Destination Clock: clk2 (R)
Logic Level : 2
Delay Ratio : 41.0% (route), 59.0% (logic)
Clock Skew : -0.175 ns
Setup Constraint : 10.000 ns
Common Path Skew : 0.173 ns
Path Slack : 9.176 ns (Passed)
Source Clock Path
<![CDATA[
{
"path_begin":
{
"type":"port",
"log_name":"Clk",
"phy_name":"Clk"
},
"path_end":
{
"type":"pin",
"log_name":"B_sig_c.ff_inst/CLK",
"phy_name":"B_sig_c.ff_inst/CLK"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"Clk",
"phy_name":"Clk"
},
"arrive":0.000,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"Clk_pad.bb_inst/B",
"phy_name":"Clk_pad.bb_inst/IOPAD"
},
"pin1":
{
"log_name":"Clk_pad.bb_inst/O",
"phy_name":"Clk_pad.bb_inst/PADDI"
},
"arrive":0.440,
"delay":0.440
},
{
"type":"net_delay",
"net":
{
"log_name":"MyPLL/lscc_pll_inst/Clk_c",
"phy_name":"Clk_c"
},
"arrive":0.766,
"delay":0.326
},
{
"type":"site_delay",
"pin0":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
},
"pin1":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS"
},
"arrive":0.766,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
},
"pin1":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS"
},
"arrive":0.766,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"MyPLL/lscc_pll_inst/clk2",
"phy_name":"clk2"
},
"arrive":3.452,
"delay":2.686
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":3.452,
"delay":0.000
}
]
}
]]>
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ---------------- ---------------- --------- --------------------- ------
Clk top CLOCK LATENCY 0.000 0.000 1
Clk NET DELAY 0.000 0.000 1
Clk_pad.bb_inst/B->Clk_pad.bb_inst/O SEIO18A_CORE_K15 PADI_DEL 0.440 0.440 1
MyPLL/lscc_pll_inst/Clk_c NET DELAY 0.326 0.766 1
MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS
PLL_CORE_PLL_LLC 0.000 0.766 2
MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS (TOTAL_ADJUSTMENTS)
PLL_CORE_PLL_LLC 0.000 0.766 2
MyPLL/lscc_pll_inst/clk2 NET DELAY 2.686 3.452 2
B_sig_c.ff_inst/CLK CLOCK PIN 0.000 3.452 1
Data Path
<![CDATA[
{
"path_begin":
{
"type":"pin",
"log_name":"B_sig_c.ff_inst/Q",
"phy_name":"B_sig_c.ff_inst/Q0"
},
"path_end":
{
"type":"pin",
"log_name":"B_sig1.ff_inst/DF",
"phy_name":"B_sig1.ff_inst/M0"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"B_sig_c.ff_inst/CLK",
"phy_name":"B_sig_c.ff_inst/CLK"
},
"pin1":
{
"log_name":"B_sig_c.ff_inst/Q",
"phy_name":"B_sig_c.ff_inst/Q0"
},
"arrive":3.745,
"delay":0.293
},
{
"type":"net_delay",
"net":
{
"log_name":"B_sig",
"phy_name":"B_sig"
},
"arrive":3.986,
"delay":0.241
},
{
"type":"site_delay",
"pin0":
{
"log_name":"i8_2_lut/A",
"phy_name":"i8_2_lut/B0"
},
"pin1":
{
"log_name":"i8_2_lut/Z",
"phy_name":"i8_2_lut/F0"
},
"arrive":4.199,
"delay":0.213
},
{
"type":"net_delay",
"net":
{
"log_name":"out2_c_N_1",
"phy_name":"out2_c_N_1"
},
"arrive":4.309,
"delay":0.110
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":4.309,
"delay":0.000
}
]
}
]]>
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ---------------- ---------------- --------- --------------------- ------
B_sig_c.ff_inst/CLK->B_sig_c.ff_inst/Q SLICE_R50C100C REG_DEL 0.293 3.745 1
B_sig NET DELAY 0.241 3.986 1
i8_2_lut/A->i8_2_lut/Z SLICE_R50C100B CTOF_DEL 0.213 4.199 1
out2_c_N_1 NET DELAY 0.110 4.309 1
B_sig1.ff_inst/DF ENDPOINT 0.000 4.309 1
Destination Clock Path
<![CDATA[
{
"path_begin":
{
"type":"port",
"log_name":"Clk",
"phy_name":"Clk"
},
"path_end":
{
"type":"pin",
"log_name":"B_sig1.ff_inst/CLK",
"phy_name":"B_sig1.ff_inst/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":10.000,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"Clk",
"phy_name":"Clk"
},
"arrive":10.000,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"Clk_pad.bb_inst/B",
"phy_name":"Clk_pad.bb_inst/IOPAD"
},
"pin1":
{
"log_name":"Clk_pad.bb_inst/O",
"phy_name":"Clk_pad.bb_inst/PADDI"
},
"arrive":10.440,
"delay":0.440
},
{
"type":"net_delay",
"net":
{
"log_name":"MyPLL/lscc_pll_inst/Clk_c",
"phy_name":"Clk_c"
},
"arrive":10.746,
"delay":0.306
},
{
"type":"site_delay",
"pin0":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
},
"pin1":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS"
},
"arrive":10.746,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
},
"pin1":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS"
},
"arrive":10.746,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"MyPLL/lscc_pll_inst/clk2",
"phy_name":"clk2"
},
"arrive":13.277,
"delay":2.531
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":13.277,
"delay":0.000
}
]
}
]]>
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ---------------- ---------------- --------- --------------------- ------
CONSTRAINT 0.000 10.000 1
Clk top CLOCK LATENCY 0.000 10.000 1
Clk NET DELAY 0.000 10.000 1
Clk_pad.bb_inst/B->Clk_pad.bb_inst/O SEIO18A_CORE_K15 PADI_DEL 0.440 10.440 1
MyPLL/lscc_pll_inst/Clk_c NET DELAY 0.306 10.746 1
MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS
PLL_CORE_PLL_LLC 0.000 10.746 2
MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS (TOTAL_ADJUSTMENTS)
PLL_CORE_PLL_LLC 0.000 10.746 2
MyPLL/lscc_pll_inst/clk2 NET DELAY 2.531 13.277 2
B_sig1.ff_inst/CLK CLOCK PIN 0.000 13.277 1
Uncertainty -(0.000) 13.277
Common Path Skew 0.173 13.450
Setup time -(-0.035) 13.485
---------------------------------------- ---------------- ---------------- --------- --------------------- ------
Required Time 13.485
Arrival Time -(4.309)
---------------------------------------- ---------------- ---------------- --------- --------------------- ------
Path Slack (Passed) 9.176
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
End of Detailed Report for timing paths
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
##########################################################
4 Hold at Speed Grade m Corner at 0 Degrees
4.1 Endpoint slacks
-------------------------------------------------------
Listing 2 End Points | Slack
-------------------------------------------------------
B_sig1.ff_inst/DF | 0.352 ns
A_Sig1.ff_inst/DF | 1.419 ns
-------------------------------------------------------
|
Hold # of endpoints with negative slack: | 0
|
-------------------------------------------------------
4.2 Detailed Report
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
Detail report of critical paths
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Detailed Report for timing paths
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++++Path 1 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : B_sig_c.ff_inst/Q (SLICE_R50C100C)
Path End : B_sig1.ff_inst/DF (SLICE_R50C100D)
Source Clock : clk2 (R)
Destination Clock: clk2 (R)
Logic Level : 2
Delay Ratio : 35.8% (route), 64.2% (logic)
Clock Skew : 0.136 ns
Hold Constraint : 0.000 ns
Common Path Skew : -0.135 ns
Path Slack : 0.352 ns (Passed)
Source Clock Path
<![CDATA[
{
"path_begin":
{
"type":"port",
"log_name":"Clk",
"phy_name":"Clk"
},
"path_end":
{
"type":"pin",
"log_name":"B_sig_c.ff_inst/CLK",
"phy_name":"B_sig_c.ff_inst/CLK"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"Clk",
"phy_name":"Clk"
},
"arrive":0.000,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"Clk_pad.bb_inst/B",
"phy_name":"Clk_pad.bb_inst/IOPAD"
},
"pin1":
{
"log_name":"Clk_pad.bb_inst/O",
"phy_name":"Clk_pad.bb_inst/PADDI"
},
"arrive":0.366,
"delay":0.366
},
{
"type":"net_delay",
"net":
{
"log_name":"MyPLL/lscc_pll_inst/Clk_c",
"phy_name":"Clk_c"
},
"arrive":0.606,
"delay":0.240
},
{
"type":"site_delay",
"pin0":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
},
"pin1":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS"
},
"arrive":0.606,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
},
"pin1":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS"
},
"arrive":0.606,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"MyPLL/lscc_pll_inst/clk2",
"phy_name":"clk2"
},
"arrive":2.483,
"delay":1.877
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":2.483,
"delay":0.000
}
]
}
]]>
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ---------------- ---------------- ------ --------------------- ------
Clk top CLOCK LATENCY 0.000 0.000 1
Clk NET DELAY 0.000 0.000 1
Clk_pad.bb_inst/B->Clk_pad.bb_inst/O SEIO18A_CORE_K15 PADI_DEL 0.366 0.366 1
MyPLL/lscc_pll_inst/Clk_c NET DELAY 0.240 0.606 1
MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS
PLL_CORE_PLL_LLC 0.000 0.606 2
MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS (TOTAL_ADJUSTMENTS)
PLL_CORE_PLL_LLC 0.000 0.606 2
MyPLL/lscc_pll_inst/clk2 NET DELAY 1.877 2.483 2
B_sig_c.ff_inst/CLK CLOCK PIN 0.000 2.483 1
Data Path
<![CDATA[
{
"path_begin":
{
"type":"pin",
"log_name":"B_sig_c.ff_inst/Q",
"phy_name":"B_sig_c.ff_inst/Q0"
},
"path_end":
{
"type":"pin",
"log_name":"B_sig1.ff_inst/DF",
"phy_name":"B_sig1.ff_inst/M0"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"B_sig_c.ff_inst/CLK",
"phy_name":"B_sig_c.ff_inst/CLK"
},
"pin1":
{
"log_name":"B_sig_c.ff_inst/Q",
"phy_name":"B_sig_c.ff_inst/Q0"
},
"arrive":2.656,
"delay":0.173
},
{
"type":"net_delay",
"net":
{
"log_name":"B_sig",
"phy_name":"B_sig"
},
"arrive":2.771,
"delay":0.115
},
{
"type":"site_delay",
"pin0":
{
"log_name":"i8_2_lut/A",
"phy_name":"i8_2_lut/B0"
},
"pin1":
{
"log_name":"i8_2_lut/Z",
"phy_name":"i8_2_lut/F0"
},
"arrive":2.887,
"delay":0.116
},
{
"type":"net_delay",
"net":
{
"log_name":"out2_c_N_1",
"phy_name":"out2_c_N_1"
},
"arrive":2.933,
"delay":0.046
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":2.933,
"delay":0.000
}
]
}
]]>
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ---------------- ---------------- ------ --------------------- ------
B_sig_c.ff_inst/CLK->B_sig_c.ff_inst/Q SLICE_R50C100C REG_DEL 0.173 2.656 1
B_sig NET DELAY 0.115 2.771 1
i8_2_lut/A->i8_2_lut/Z SLICE_R50C100B CTOF_DEL 0.116 2.887 1
out2_c_N_1 NET DELAY 0.046 2.933 1
B_sig1.ff_inst/DF ENDPOINT 0.000 2.933 1
Destination Clock Path
<![CDATA[
{
"path_begin":
{
"type":"port",
"log_name":"Clk",
"phy_name":"Clk"
},
"path_end":
{
"type":"pin",
"log_name":"B_sig1.ff_inst/CLK",
"phy_name":"B_sig1.ff_inst/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":0.000,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"Clk",
"phy_name":"Clk"
},
"arrive":0.000,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"Clk_pad.bb_inst/B",
"phy_name":"Clk_pad.bb_inst/IOPAD"
},
"pin1":
{
"log_name":"Clk_pad.bb_inst/O",
"phy_name":"Clk_pad.bb_inst/PADDI"
},
"arrive":0.366,
"delay":0.366
},
{
"type":"net_delay",
"net":
{
"log_name":"MyPLL/lscc_pll_inst/Clk_c",
"phy_name":"Clk_c"
},
"arrive":0.623,
"delay":0.257
},
{
"type":"site_delay",
"pin0":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
},
"pin1":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS"
},
"arrive":0.623,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
},
"pin1":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS"
},
"arrive":0.623,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"MyPLL/lscc_pll_inst/clk2",
"phy_name":"clk2"
},
"arrive":2.619,
"delay":1.996
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":2.619,
"delay":0.000
}
]
}
]]>
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ---------------- ---------------- ------ --------------------- ------
CONSTRAINT 0.000 0.000 1
Clk top CLOCK LATENCY 0.000 0.000 1
Clk NET DELAY 0.000 0.000 1
Clk_pad.bb_inst/B->Clk_pad.bb_inst/O SEIO18A_CORE_K15 PADI_DEL 0.366 0.366 1
MyPLL/lscc_pll_inst/Clk_c NET DELAY 0.257 0.623 1
MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS
PLL_CORE_PLL_LLC 0.000 0.623 2
MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS (TOTAL_ADJUSTMENTS)
PLL_CORE_PLL_LLC 0.000 0.623 2
MyPLL/lscc_pll_inst/clk2 NET DELAY 1.996 2.619 2
B_sig1.ff_inst/CLK CLOCK PIN 0.000 2.619 1
Uncertainty 0.000 2.619
Common Path Skew -0.135 2.484
Hold time 0.097 2.581
---------------------------------------- ---------------- ---------------- ------ --------------------- ------
Required Time -2.581
Arrival Time 2.933
---------------------------------------- ---------------- ---------------- ------ --------------------- ------
Path Slack (Passed) 0.352
++++ Path 2 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : A_Sig_c.ff_inst/Q (SLICE_R4C4D)
Path End : A_Sig1.ff_inst/DF (SLICE_R2C100D)
Source Clock : clk1 (R)
Destination Clock: clk1 (R)
Logic Level : 1
Delay Ratio : 88.8% (route), 11.2% (logic)
Clock Skew : 0.136 ns
Hold Constraint : 0.000 ns
Common Path Skew : -0.066 ns
Path Slack : 1.419 ns (Passed)
Source Clock Path
<![CDATA[
{
"path_begin":
{
"type":"port",
"log_name":"Clk",
"phy_name":"Clk"
},
"path_end":
{
"type":"pin",
"log_name":"A_Sig_c.ff_inst/CLK",
"phy_name":"A_Sig_c.ff_inst/CLK"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"Clk",
"phy_name":"Clk"
},
"arrive":0.000,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"Clk_pad.bb_inst/B",
"phy_name":"Clk_pad.bb_inst/IOPAD"
},
"pin1":
{
"log_name":"Clk_pad.bb_inst/O",
"phy_name":"Clk_pad.bb_inst/PADDI"
},
"arrive":0.366,
"delay":0.366
},
{
"type":"net_delay",
"net":
{
"log_name":"MyPLL/lscc_pll_inst/Clk_c",
"phy_name":"Clk_c"
},
"arrive":0.606,
"delay":0.240
},
{
"type":"site_delay",
"pin0":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
},
"pin1":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
},
"arrive":0.606,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
},
"pin1":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
},
"arrive":0.606,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"MyPLL/lscc_pll_inst/clk1",
"phy_name":"clk1"
},
"arrive":2.483,
"delay":1.877
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":2.483,
"delay":0.000
}
]
}
]]>
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ---------------- ---------------- ------ --------------------- ------
Clk top CLOCK LATENCY 0.000 0.000 1
Clk NET DELAY 0.000 0.000 1
Clk_pad.bb_inst/B->Clk_pad.bb_inst/O SEIO18A_CORE_K15 PADI_DEL 0.366 0.366 1
MyPLL/lscc_pll_inst/Clk_c NET DELAY 0.240 0.606 1
MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP
PLL_CORE_PLL_LLC 0.000 0.606 2
MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP (TOTAL_ADJUSTMENTS)
PLL_CORE_PLL_LLC 0.000 0.606 2
MyPLL/lscc_pll_inst/clk1 NET DELAY 1.877 2.483 2
A_Sig_c.ff_inst/CLK CLOCK PIN 0.000 2.483 1
Data Path
<![CDATA[
{
"path_begin":
{
"type":"pin",
"log_name":"A_Sig_c.ff_inst/Q",
"phy_name":"A_Sig_c.ff_inst/Q0"
},
"path_end":
{
"type":"pin",
"log_name":"A_Sig1.ff_inst/DF",
"phy_name":"A_Sig1.ff_inst/M0"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"A_Sig_c.ff_inst/CLK",
"phy_name":"A_Sig_c.ff_inst/CLK"
},
"pin1":
{
"log_name":"A_Sig_c.ff_inst/Q",
"phy_name":"A_Sig_c.ff_inst/Q0"
},
"arrive":2.661,
"delay":0.178
},
{
"type":"net_delay",
"net":
{
"log_name":"A_Sig",
"phy_name":"A_Sig"
},
"arrive":4.066,
"delay":1.405
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":4.066,
"delay":0.000
}
]
}
]]>
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ---------------- ---------------- ------ --------------------- ------
A_Sig_c.ff_inst/CLK->A_Sig_c.ff_inst/Q SLICE_R4C4D REG_DEL 0.178 2.661 2
A_Sig NET DELAY 1.405 4.066 2
A_Sig1.ff_inst/DF ENDPOINT 0.000 4.066 1
Destination Clock Path
<![CDATA[
{
"path_begin":
{
"type":"port",
"log_name":"Clk",
"phy_name":"Clk"
},
"path_end":
{
"type":"pin",
"log_name":"A_Sig1.ff_inst/CLK",
"phy_name":"A_Sig1.ff_inst/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":0.000,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"Clk",
"phy_name":"Clk"
},
"arrive":0.000,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"Clk_pad.bb_inst/B",
"phy_name":"Clk_pad.bb_inst/IOPAD"
},
"pin1":
{
"log_name":"Clk_pad.bb_inst/O",
"phy_name":"Clk_pad.bb_inst/PADDI"
},
"arrive":0.366,
"delay":0.366
},
{
"type":"net_delay",
"net":
{
"log_name":"MyPLL/lscc_pll_inst/Clk_c",
"phy_name":"Clk_c"
},
"arrive":0.623,
"delay":0.257
},
{
"type":"site_delay",
"pin0":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
},
"pin1":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
},
"arrive":0.623,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
},
"pin1":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
},
"arrive":0.623,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"MyPLL/lscc_pll_inst/clk1",
"phy_name":"clk1"
},
"arrive":2.619,
"delay":1.996
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":2.619,
"delay":0.000
}
]
}
]]>
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ---------------- ---------------- ------ --------------------- ------
CONSTRAINT 0.000 0.000 1
Clk top CLOCK LATENCY 0.000 0.000 1
Clk NET DELAY 0.000 0.000 1
Clk_pad.bb_inst/B->Clk_pad.bb_inst/O SEIO18A_CORE_K15 PADI_DEL 0.366 0.366 1
MyPLL/lscc_pll_inst/Clk_c NET DELAY 0.257 0.623 1
MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP
PLL_CORE_PLL_LLC 0.000 0.623 2
MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP (TOTAL_ADJUSTMENTS)
PLL_CORE_PLL_LLC 0.000 0.623 2
MyPLL/lscc_pll_inst/clk1 NET DELAY 1.996 2.619 2
A_Sig1.ff_inst/CLK CLOCK PIN 0.000 2.619 1
Uncertainty 0.000 2.619
Common Path Skew -0.066 2.553
Hold time 0.094 2.647
---------------------------------------- ---------------- ---------------- ------ --------------------- ------
Required Time -2.647
Arrival Time 4.066
---------------------------------------- ---------------- ---------------- ------ --------------------- ------
Path Slack (Passed) 1.419
++++ Path 3 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : A_Sig_c.ff_inst/Q (SLICE_R4C4D)
Path End : B_sig1.ff_inst/DF (SLICE_R50C100D)
Source Clock : clk1 (R)
Destination Clock: clk2 (R)
Logic Level : 2
Delay Ratio : 87.9% (route), 12.1% (logic)
Clock Skew : 0.136 ns
Hold Constraint : -7.500 ns
Common Path Skew : -0.016 ns
Path Slack : 9.703 ns (Passed)
Source Clock Path
<![CDATA[
{
"path_begin":
{
"type":"port",
"log_name":"Clk",
"phy_name":"Clk"
},
"path_end":
{
"type":"pin",
"log_name":"A_Sig_c.ff_inst/CLK",
"phy_name":"A_Sig_c.ff_inst/CLK"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"Clk",
"phy_name":"Clk"
},
"arrive":0.000,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"Clk_pad.bb_inst/B",
"phy_name":"Clk_pad.bb_inst/IOPAD"
},
"pin1":
{
"log_name":"Clk_pad.bb_inst/O",
"phy_name":"Clk_pad.bb_inst/PADDI"
},
"arrive":0.366,
"delay":0.366
},
{
"type":"net_delay",
"net":
{
"log_name":"MyPLL/lscc_pll_inst/Clk_c",
"phy_name":"Clk_c"
},
"arrive":0.606,
"delay":0.240
},
{
"type":"site_delay",
"pin0":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
},
"pin1":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
},
"arrive":0.606,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
},
"pin1":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP"
},
"arrive":0.606,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"MyPLL/lscc_pll_inst/clk1",
"phy_name":"clk1"
},
"arrive":2.483,
"delay":1.877
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":2.483,
"delay":0.000
}
]
}
]]>
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ---------------- ---------------- ------ --------------------- ------
Clk top CLOCK LATENCY 0.000 0.000 1
Clk NET DELAY 0.000 0.000 1
Clk_pad.bb_inst/B->Clk_pad.bb_inst/O SEIO18A_CORE_K15 PADI_DEL 0.366 0.366 1
MyPLL/lscc_pll_inst/Clk_c NET DELAY 0.240 0.606 1
MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP
PLL_CORE_PLL_LLC 0.000 0.606 2
MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOP (TOTAL_ADJUSTMENTS)
PLL_CORE_PLL_LLC 0.000 0.606 2
MyPLL/lscc_pll_inst/clk1 NET DELAY 1.877 2.483 2
A_Sig_c.ff_inst/CLK CLOCK PIN 0.000 2.483 1
Data Path
<![CDATA[
{
"path_begin":
{
"type":"pin",
"log_name":"A_Sig_c.ff_inst/Q",
"phy_name":"A_Sig_c.ff_inst/Q0"
},
"path_end":
{
"type":"pin",
"log_name":"B_sig1.ff_inst/DF",
"phy_name":"B_sig1.ff_inst/M0"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"A_Sig_c.ff_inst/CLK",
"phy_name":"A_Sig_c.ff_inst/CLK"
},
"pin1":
{
"log_name":"A_Sig_c.ff_inst/Q",
"phy_name":"A_Sig_c.ff_inst/Q0"
},
"arrive":2.661,
"delay":0.178
},
{
"type":"net_delay",
"net":
{
"log_name":"A_Sig",
"phy_name":"A_Sig"
},
"arrive":4.741,
"delay":2.080
},
{
"type":"site_delay",
"pin0":
{
"log_name":"i8_2_lut/B",
"phy_name":"i8_2_lut/D0"
},
"pin1":
{
"log_name":"i8_2_lut/Z",
"phy_name":"i8_2_lut/F0"
},
"arrive":4.857,
"delay":0.116
},
{
"type":"net_delay",
"net":
{
"log_name":"out2_c_N_1",
"phy_name":"out2_c_N_1"
},
"arrive":4.903,
"delay":0.046
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":4.903,
"delay":0.000
}
]
}
]]>
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ---------------- ---------------- ------ --------------------- ------
A_Sig_c.ff_inst/CLK->A_Sig_c.ff_inst/Q SLICE_R4C4D REG_DEL 0.178 2.661 2
A_Sig NET DELAY 2.080 4.741 2
i8_2_lut/B->i8_2_lut/Z SLICE_R50C100B CTOF_DEL 0.116 4.857 1
out2_c_N_1 NET DELAY 0.046 4.903 1
B_sig1.ff_inst/DF ENDPOINT 0.000 4.903 1
Destination Clock Path
<![CDATA[
{
"path_begin":
{
"type":"port",
"log_name":"Clk",
"phy_name":"Clk"
},
"path_end":
{
"type":"pin",
"log_name":"B_sig1.ff_inst/CLK",
"phy_name":"B_sig1.ff_inst/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":-7.500,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"Clk",
"phy_name":"Clk"
},
"arrive":-7.500,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"Clk_pad.bb_inst/B",
"phy_name":"Clk_pad.bb_inst/IOPAD"
},
"pin1":
{
"log_name":"Clk_pad.bb_inst/O",
"phy_name":"Clk_pad.bb_inst/PADDI"
},
"arrive":-7.134,
"delay":0.366
},
{
"type":"net_delay",
"net":
{
"log_name":"MyPLL/lscc_pll_inst/Clk_c",
"phy_name":"Clk_c"
},
"arrive":-6.877,
"delay":0.257
},
{
"type":"site_delay",
"pin0":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
},
"pin1":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS"
},
"arrive":-6.877,
"delay":0.000
},
{
"type":"site_delay",
"pin0":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/REFCK"
},
"pin1":
{
"log_name":"MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS",
"phy_name":"MyPLL.lscc_pll_inst.gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS"
},
"arrive":-6.877,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"MyPLL/lscc_pll_inst/clk2",
"phy_name":"clk2"
},
"arrive":-4.881,
"delay":1.996
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":-4.881,
"delay":0.000
}
]
}
]]>
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ---------------- ---------------- ------ --------------------- ------
CONSTRAINT 0.000 -7.500 1
Clk top CLOCK LATENCY 0.000 -7.500 1
Clk NET DELAY 0.000 -7.500 1
Clk_pad.bb_inst/B->Clk_pad.bb_inst/O SEIO18A_CORE_K15 PADI_DEL 0.366 -7.134 1
MyPLL/lscc_pll_inst/Clk_c NET DELAY 0.257 -6.877 1
MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS
PLL_CORE_PLL_LLC 0.000 -6.877 2
MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/REFCK->MyPLL/lscc_pll_inst/gen_no_refclk_mon.u_PLL.PLL_inst/CLKOS (TOTAL_ADJUSTMENTS)
PLL_CORE_PLL_LLC 0.000 -6.877 2
MyPLL/lscc_pll_inst/clk2 NET DELAY 1.996 -4.881 2
B_sig1.ff_inst/CLK CLOCK PIN 0.000 -4.881 1
Uncertainty 0.000 -4.881
Common Path Skew -0.016 -4.897
Hold time 0.097 -4.800
---------------------------------------- ---------------- ---------------- ------ --------------------- ------
Required Time 4.800
Arrival Time 4.903
---------------------------------------- ---------------- ---------------- ------ --------------------- ------
Path Slack (Passed) 9.703
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
End of Detailed Report for timing paths
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
##########################################################