@N: MF916 |Option synthesis_strategy=base is enabled. 
@N: MF248 |Running in 64-bit mode.
@N: MF667 |Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.)
@N: BZ173 :"d:\02_lscc\13_vhdl\lab05\lab05\source\impl_1\decoder_7seg.vhd":16:8:16:9|ROM decoder_inst1.seg_out_1[6:0] (in view: work.top_level(behavioral)) mapped in logic.
@N: BZ173 :"d:\02_lscc\13_vhdl\lab05\lab05\source\impl_1\decoder_7seg.vhd":16:8:16:9|ROM decoder_inst1.seg_out_1[6:0] (in view: work.top_level(behavioral)) mapped in logic.
@N: MO106 :"d:\02_lscc\13_vhdl\lab05\lab05\source\impl_1\decoder_7seg.vhd":16:8:16:9|Found ROM decoder_inst1.seg_out_1[6:0] (in view: work.top_level(behavioral)) with 16 words by 7 bits.
@N: MO230 :"d:\02_lscc\13_vhdl\lab05\lab05\source\impl_1\cnt24.vhd":24:8:24:9|Found up-down counter in view:work.top_level(behavioral) instance counter_inst.cnt_reg[17:0]  
@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  
@N: BW103 |The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns.
@N: BW107 |Synopsys Constraint File capacitance units using default value of 1pF 
@N: MT615 |Found clock clk2 with period 1000.00ns 
@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
