m255
K4
z2
!s11e vcom 2023.3 2023.07, Jul 18 2023
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!s112 1.1
!i10d 8192
!i10e 25
!i10f 100
cModel Technology
Z0 dD:/02_LSCC/13_VHDL/LAB04/LAB04/Sim001
Ecounter_fsm
Z1 w1724229223
Z2 DPx4 ieee 18 std_logic_unsigned 0 22 o4hn5gYc0WVo72BSL@Ta50
Z3 DPx4 ieee 15 std_logic_arith 0 22 B[jVX6I8iRX2o6WYW0BB>3
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Z5 DPx4 ieee 14 std_logic_1164 0 22 6<US`=mgl_dFdCEFF7J=m1
!i122 2
R0
Z6 8D:/02_LSCC/13_VHDL/LAB04/LAB04/source/impl_1/FSM.vhd
Z7 FD:/02_LSCC/13_VHDL/LAB04/LAB04/source/impl_1/FSM.vhd
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!i10b 1
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Z11 !s90 -reportprogress|300|-work|work|-2002|-explicit|-stats=none|D:/02_LSCC/13_VHDL/LAB04/LAB04/source/impl_1/FSM.vhd|
Z12 !s107 D:/02_LSCC/13_VHDL/LAB04/LAB04/source/impl_1/FSM.vhd|
!i113 1
Z13 o-work work -2002 -explicit -O0
Z14 tExplicit 1 CvgOpt 0
Abehavioral
R2
R3
R4
R5
DEx4 work 11 counter_fsm 0 22 QJF^IjYz_UTQJRE5W<JcJ1
!i122 2
l23
L18 42
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32
R9
!i10b 1
R10
R11
R12
!i113 1
R13
R14
Etestbench
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Z16 DPx4 ieee 11 numeric_std 0 22 F8@]:i<mFK7<TjIzKcTGi0
R4
R5
!i122 3
R0
Z17 8D:/02_LSCC/13_VHDL/LAB04/LAB04/counter_fsm_tb.vhd
Z18 FD:/02_LSCC/13_VHDL/LAB04/LAB04/counter_fsm_tb.vhd
l0
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R8
32
R9
!i10b 1
R10
Z19 !s90 -reportprogress|300|-work|work|-2002|-explicit|-stats=none|D:/02_LSCC/13_VHDL/LAB04/LAB04/counter_fsm_tb.vhd|
Z20 !s107 D:/02_LSCC/13_VHDL/LAB04/LAB04/counter_fsm_tb.vhd|
!i113 1
R13
R14
Abehavior
R16
R4
R5
DEx4 work 9 testbench 0 22 @4A@N>j4WBG9:6AQL7S^F0
!i122 3
l56
L28 49
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!s100 W2Jo27MffH8<GSi9>^W_Q3
R8
32
R9
!i10b 1
R10
R19
R20
!i113 1
R13
R14
