# Reading pref.tcl
# do D:/02_LSCC/13_VHDL/LAB04/LAB04/Sim001/Sim001.mdo
# Loading project Sim001
# Compile of FSM.vhd was successful.
# Compile of counter_fsm_tb.vhd was successful.
# 2 compiles, 0 failed with no errors.
# vsim -L work -L pmi_work -L ovi_lfcpnx -suppress vsim-7033,vsim-8630,3009,3389 testbench 
# Start time: 09:39:19 on Aug 21,2024
# //  ModelSim - Lattice FPGA Edition 2023.3 Jul 18 2023
# //
# //  Copyright 1991-2023 Mentor Graphics Corporation
# //  All Rights Reserved.
# //
# //  ModelSim - Lattice FPGA Edition and its associated documentation contain trade
# //  secrets and commercial or financial information that are the property of
# //  Mentor Graphics Corporation and are privileged, confidential,
# //  and exempt from disclosure under the Freedom of Information Act,
# //  5 U.S.C. Section 552. Furthermore, this information
# //  is prohibited from disclosure under the Trade Secrets Act,
# //  18 U.S.C. Section 1905.
# //
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading ieee.numeric_std(body)
# Loading work.testbench(behavior)
# Loading ovi_lfcpnx.GSR
# Loading ovi_lfcpnx.GSR_CORE
# Loading ovi_lfcpnx.gsr_center
# Loading ovi_lfcpnx.VHI
# Loading ovi_lfcpnx.VLO
# Loading ieee.std_logic_arith(body)
# Loading ieee.std_logic_unsigned(body)
# Loading work.counter_fsm(behavioral)
# ** Warning: (vsim-3934) [TFMPC] - Missing VHDL connection for formal Verilog port 'CLK'.
#    Time: 0 ps  Iteration: 0  Instance: /testbench/GSR_INST File: D:/02_LSCC/13_VHDL/LAB04/LAB04/counter_fsm_tb.vhd Line: 58
# .main_pane.wave.interior.cs.body.pw.wf
# End time: 10:01:38 on Aug 21,2024, Elapsed time: 0:22:19
# Errors: 0, Warnings: 3
