m255
K4
z2
!s11e vcom 2023.3 2023.07, Jul 18 2023
13
!s112 1.1
!i10d 8192
!i10e 25
!i10f 100
cModel Technology
Z0 dD:/02_LSCC/13_VHDL/LAB01/LAB01/Sim001
Eseven_segment_decoder
Z1 w1724062241
Z2 DPx3 std 6 textio 0 22 LS[?81n5ZHWBI9JkBZTV<2
Z3 DPx4 ieee 14 std_logic_1164 0 22 6<US`=mgl_dFdCEFF7J=m1
!i122 0
R0
Z4 8D:/02_LSCC/13_VHDL/LAB01/LAB01/source/impl_1/Decoder_7Seg.vhd
Z5 FD:/02_LSCC/13_VHDL/LAB01/LAB01/source/impl_1/Decoder_7Seg.vhd
l0
L5 1
V?Q]DfM=dG[dmBjf=RThn80
!s100 dlbUAhOKZcKl2g01j[5f_3
Z6 OT;C;2023.3;77
32
Z7 !s110 1724226270
!i10b 1
Z8 !s108 1724226270.000000
Z9 !s90 -reportprogress|300|-work|work|D:/02_LSCC/13_VHDL/LAB01/LAB01/source/impl_1/Decoder_7Seg.vhd|
Z10 !s107 D:/02_LSCC/13_VHDL/LAB01/LAB01/source/impl_1/Decoder_7Seg.vhd|
!i113 1
Z11 o-work work -O0
Z12 tExplicit 1 CvgOpt 0
Abehavioral
R2
R3
DEx4 work 21 seven_segment_decoder 0 22 ?Q]DfM=dG[dmBjf=RThn80
!i122 0
l14
L13 21
V0;PK0>Ngi4L1Y_0F]DNFG3
!s100 _aA7FeQ=nK@g5Q?U<QMNU2
R6
32
R7
!i10b 1
R8
R9
R10
!i113 1
R11
R12
Etestbench
Z13 w1724226254
Z14 DPx4 ieee 11 numeric_std 0 22 F8@]:i<mFK7<TjIzKcTGi0
R2
R3
!i122 1
R0
Z15 8D:/02_LSCC/13_VHDL/LAB01/LAB01/seven_segment_decoder_tb.vhd
Z16 FD:/02_LSCC/13_VHDL/LAB01/LAB01/seven_segment_decoder_tb.vhd
l0
L25 1
V6@JCiGGLMD_MBEP9CTQ9<0
!s100 ]60MdhTbP@iNUdGn015ih2
R6
32
R7
!i10b 1
R8
Z17 !s90 -reportprogress|300|-work|work|D:/02_LSCC/13_VHDL/LAB01/LAB01/seven_segment_decoder_tb.vhd|
!s107 D:/02_LSCC/13_VHDL/LAB01/LAB01/seven_segment_decoder_tb.vhd|
!i113 1
R11
R12
Abehavior
R14
R2
R3
DEx4 work 9 testbench 0 22 6@JCiGGLMD_MBEP9CTQ9<0
!i122 1
l46
L28 44
Vi@`4c5mf0c353^?]onI0d0
!s100 @gd4Yki57Q8YHWY`FJEJE3
R6
32
R7
!i10b 1
R8
R17
Z18 !s107 D:/02_LSCC/13_VHDL/LAB01/LAB01/seven_segment_decoder_tb.vhd|
!i113 1
R11
R12
