# Reading pref.tcl
# do D:/02_LSCC/13_VHDL/LAB03/LAB03/Sim001/Sim001.mdo
# Loading project Sim001
# Model Technology ModelSim - Lattice FPGA Edition vcom 2023.3 Compiler 2023.07 Jul 18 2023
# Start time: 09:27:26 on Aug 21,2024
# vcom -reportprogress 300 -work work D:/02_LSCC/13_VHDL/LAB03/LAB03/source/impl_1/CNT24.vhd 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package STD_LOGIC_UNSIGNED
# -- Compiling entity Gen_CNT
# -- Compiling architecture Behavioral of Gen_CNT
# End time: 09:27:26 on Aug 21,2024, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Lattice FPGA Edition vcom 2023.3 Compiler 2023.07 Jul 18 2023
# Start time: 09:27:26 on Aug 21,2024
# vcom -reportprogress 300 -work work D:/02_LSCC/13_VHDL/LAB03/LAB03/Gen_CNT_tb.vhd 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity testbench
# -- Compiling architecture behavior of testbench
# End time: 09:27:26 on Aug 21,2024, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vsim -L work -L pmi_work -L ovi_lfcpnx -suppress vsim-7033,vsim-8630,3009,3389 testbench 
# Start time: 09:27:26 on Aug 21,2024
# //  ModelSim - Lattice FPGA Edition 2023.3 Jul 18 2023
# //
# //  Copyright 1991-2023 Mentor Graphics Corporation
# //  All Rights Reserved.
# //
# //  ModelSim - Lattice FPGA Edition and its associated documentation contain trade
# //  secrets and commercial or financial information that are the property of
# //  Mentor Graphics Corporation and are privileged, confidential,
# //  and exempt from disclosure under the Freedom of Information Act,
# //  5 U.S.C. Section 552. Furthermore, this information
# //  is prohibited from disclosure under the Trade Secrets Act,
# //  18 U.S.C. Section 1905.
# //
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading ieee.numeric_std(body)
# Loading work.testbench(behavior)
# Loading ovi_lfcpnx.GSR
# Loading ovi_lfcpnx.GSR_CORE
# Loading ovi_lfcpnx.gsr_center
# Loading ovi_lfcpnx.VHI
# Loading ovi_lfcpnx.VLO
# Loading ieee.std_logic_arith(body)
# Loading ieee.std_logic_unsigned(body)
# Loading work.gen_cnt(behavioral)
# ** Warning: (vsim-3934) [TFMPC] - Missing VHDL connection for formal Verilog port 'CLK'.
#    Time: 0 ps  Iteration: 0  Instance: /testbench/GSR_INST File: D:/02_LSCC/13_VHDL/LAB03/LAB03/Gen_CNT_tb.vhd Line: 52
# .main_pane.wave.interior.cs.body.pw.wf
# End time: 09:28:03 on Aug 21,2024, Elapsed time: 0:00:37
# Errors: 0, Warnings: 6
