m255
K4
z2
!s11e vcom 2023.3 2023.07, Jul 18 2023
13
!s112 1.1
!i10d 8192
!i10e 25
!i10f 100
cModel Technology
Z0 dD:/02_LSCC/13_VHDL/LAB05/LAB05/Sim001
Ecounter_fsm
Z1 w1724229223
Z2 DPx4 ieee 18 std_logic_unsigned 0 22 o4hn5gYc0WVo72BSL@Ta50
Z3 DPx4 ieee 15 std_logic_arith 0 22 B[jVX6I8iRX2o6WYW0BB>3
Z4 DPx3 std 6 textio 0 22 LS[?81n5ZHWBI9JkBZTV<2
Z5 DPx4 ieee 14 std_logic_1164 0 22 6<US`=mgl_dFdCEFF7J=m1
!i122 7
R0
Z6 8D:/02_LSCC/13_VHDL/LAB05/LAB05/source/impl_1/FSM.vhd
Z7 FD:/02_LSCC/13_VHDL/LAB05/LAB05/source/impl_1/FSM.vhd
l0
L7 1
VQJF^IjYz_UTQJRE5W<JcJ1
!s100 AcYXH8be^LaI3XF^KCFlK0
Z8 OT;C;2023.3;77
32
Z9 !s110 1724230925
!i10b 1
Z10 !s108 1724230925.000000
Z11 !s90 -reportprogress|300|-work|work|-2002|-explicit|-stats=none|D:/02_LSCC/13_VHDL/LAB05/LAB05/source/impl_1/FSM.vhd|
Z12 !s107 D:/02_LSCC/13_VHDL/LAB05/LAB05/source/impl_1/FSM.vhd|
!i113 1
Z13 o-work work -2002 -explicit -O0
Z14 tExplicit 1 CvgOpt 0
Abehavioral
R2
R3
R4
R5
DEx4 work 11 counter_fsm 0 22 QJF^IjYz_UTQJRE5W<JcJ1
!i122 7
l23
L18 42
VcSf;KTGnz1;l_jMhL_PJc1
!s100 =;1TMY[_el2lTTMNW?cZm1
R8
32
R9
!i10b 1
R10
R11
R12
!i113 1
R13
R14
Egen_cnt
Z15 w1724228795
R2
R3
R4
R5
!i122 6
R0
Z16 8D:/02_LSCC/13_VHDL/LAB05/LAB05/source/impl_1/CNT24.vhd
Z17 FD:/02_LSCC/13_VHDL/LAB05/LAB05/source/impl_1/CNT24.vhd
l0
L7 1
V6bVZ51JVa;m=H6BkM?LFB3
!s100 c@@M6k8Un0bGW<N32HONn3
R8
32
R9
!i10b 1
R10
Z18 !s90 -reportprogress|300|-work|work|-2002|-explicit|-stats=none|D:/02_LSCC/13_VHDL/LAB05/LAB05/source/impl_1/CNT24.vhd|
Z19 !s107 D:/02_LSCC/13_VHDL/LAB05/LAB05/source/impl_1/CNT24.vhd|
!i113 1
R13
R14
Abehavioral
R2
R3
R4
R5
DEx4 work 7 gen_cnt 0 22 6bVZ51JVa;m=H6BkM?LFB3
!i122 6
l20
L18 18
V9?c>o1UiTOcmb9;<cb;2E3
!s100 ;cFBRmZHbRi=9nn48`Ofa0
R8
32
R9
!i10b 1
R10
R18
R19
!i113 1
R13
R14
Pmypackage
R4
R5
!i122 8
Z20 w1724230446
R0
Z21 8D:/02_LSCC/13_VHDL/LAB05/LAB05/source/impl_1/MyPackage.vhd
Z22 FD:/02_LSCC/13_VHDL/LAB05/LAB05/source/impl_1/MyPackage.vhd
l0
L4 41
VSGK<91hT^Bh`0NF<fmTi`2
!s100 3KYj4_AFA8bD]<ceF=>=]2
R8
32
b1
R9
!i10b 1
R10
Z23 !s90 -reportprogress|300|-work|work|-2002|-explicit|-stats=none|D:/02_LSCC/13_VHDL/LAB05/LAB05/source/impl_1/MyPackage.vhd|
Z24 !s107 D:/02_LSCC/13_VHDL/LAB05/LAB05/source/impl_1/MyPackage.vhd|
!i113 1
R13
R14
Bbody
Z25 DPx4 work 9 mypackage 0 22 SGK<91hT^Bh`0NF<fmTi`2
R4
R5
!i122 8
l0
L47 28
Vhl5kN21kTeRRQHEHeC3i21
!s100 Z7=2]9@amg6NDn@m3eJ]R3
R8
32
R9
!i10b 1
R10
R23
R24
!i113 1
R13
R14
Eseven_segment_decoder
Z26 w1724062241
R4
R5
!i122 10
R0
Z27 8D:/02_LSCC/13_VHDL/LAB05/LAB05/source/impl_1/Decoder_7Seg.vhd
Z28 FD:/02_LSCC/13_VHDL/LAB05/LAB05/source/impl_1/Decoder_7Seg.vhd
l0
L5 1
Vhe_JWm@7:Mom^7]h5N;A@0
!s100 dlbUAhOKZcKl2g01j[5f_3
R8
32
R9
!i10b 1
R10
Z29 !s90 -reportprogress|300|-work|work|-2002|-explicit|-stats=none|D:/02_LSCC/13_VHDL/LAB05/LAB05/source/impl_1/Decoder_7Seg.vhd|
Z30 !s107 D:/02_LSCC/13_VHDL/LAB05/LAB05/source/impl_1/Decoder_7Seg.vhd|
!i113 1
R13
R14
Abehavioral
R4
R5
DEx4 work 21 seven_segment_decoder 0 22 he_JWm@7:Mom^7]h5N;A@0
!i122 10
l14
L13 21
V5fFbf1T7_NB`zz13T^VVE0
!s100 _aA7FeQ=nK@g5Q?U<QMNU2
R8
32
R9
!i10b 1
R10
R29
R30
!i113 1
R13
R14
Etestbench
Z31 w1724230858
Z32 DPx4 ieee 11 numeric_std 0 22 F8@]:i<mFK7<TjIzKcTGi0
R4
R5
!i122 11
R0
Z33 8D:/02_LSCC/13_VHDL/LAB05/LAB05/top_level_tb.vhd
Z34 FD:/02_LSCC/13_VHDL/LAB05/LAB05/top_level_tb.vhd
l0
L25 1
V@4A@N>j4WBG9:6AQL7S^F0
!s100 ]60MdhTbP@iNUdGn015ih2
R8
32
R9
!i10b 1
R10
Z35 !s90 -reportprogress|300|-work|work|-2002|-explicit|-stats=none|D:/02_LSCC/13_VHDL/LAB05/LAB05/top_level_tb.vhd|
Z36 !s107 D:/02_LSCC/13_VHDL/LAB05/LAB05/top_level_tb.vhd|
!i113 1
R13
R14
Abehavior
R32
R4
R5
DEx4 work 9 testbench 0 22 @4A@N>j4WBG9:6AQL7S^F0
!i122 11
l50
Z37 L28 50
V>9;_kUA03RSB?TNhS>9nE0
Z38 !s100 zebk]N0m_`KGeZ7N9Uk0B1
R8
32
R9
!i10b 1
R10
R35
R36
!i113 1
R13
R14
Etop_level
Z39 w1724230659
R25
R2
R3
R4
R5
!i122 9
R0
Z40 8D:/02_LSCC/13_VHDL/LAB05/LAB05/source/impl_1/top.vhd
Z41 FD:/02_LSCC/13_VHDL/LAB05/LAB05/source/impl_1/top.vhd
l0
L7 1
VOXNTh?BHG4c?`f`S2FbZ_1
!s100 3dC=m3iU>H?;0hZNSK:z]2
R8
32
R9
!i10b 1
R10
Z42 !s90 -reportprogress|300|-work|work|-2002|-explicit|-stats=none|D:/02_LSCC/13_VHDL/LAB05/LAB05/source/impl_1/top.vhd|
Z43 !s107 D:/02_LSCC/13_VHDL/LAB05/LAB05/source/impl_1/top.vhd|
!i113 1
R13
R14
Abehavioral
R25
R2
R3
R4
R5
DEx4 work 9 top_level 0 22 OXNTh?BHG4c?`f`S2FbZ_1
!i122 9
l38
L15 95
VII4;946?Azje]dVNN79IG3
!s100 H8^b@hUFKWzk8jfHMdDgl2
R8
32
R9
!i10b 1
R10
R42
R43
!i113 1
R13
R14
