<?xml version="1.0" encoding="UTF-8"?>
<BuildStatus>
    <Strategy name="Strategy1">
        <Milestone name="Export" build_result="0" build_time="0">
            <Task name="Bitgen" build_result="0" update_result="3" update_time="0"/>
            <Task name="IBIS" build_result="0" update_result="3" update_time="0"/>
            <Task name="TimingSimFileVlg" build_result="0" update_result="3" update_time="0"/>
        </Milestone>
        <Milestone name="Map" build_result="0" build_time="0">
            <Task name="Map" build_result="0" update_result="3" update_time="0"/>
            <Task name="MapTrace" build_result="0" update_result="3" update_time="0"/>
        </Milestone>
        <Milestone name="PAR" build_result="0" build_time="0">
            <Task name="PAR" build_result="0" update_result="3" update_time="0"/>
            <Task name="PARTrace" build_result="0" update_result="3" update_time="0"/>
            <Task name="IOTiming" build_result="0" update_result="3" update_time="0"/>
        </Milestone>
        <Milestone name="Synthesis" build_result="0" build_time="1724228795">
            <Task name="Synplify_Synthesis" build_result="0" update_result="2" update_time="1724228795"/>
            <Task name="SynTrace" build_result="0" update_result="2" update_time="1724228222"/>
            <Task name="SynVerilogSimFile" build_result="0" update_result="2" update_time="1724228222"/>
            <Task name="LSE_Compile" build_result="0" update_result="2" update_time="1724228222"/>
        </Milestone>
        <Report name="LAB03_impl_1_syn.udb" last_build_time="1724228614" last_build_size="3328"/>
    </Strategy>
</BuildStatus>
