@N: MF916 |Option synthesis_strategy=base is enabled. 
@N: MF248 |Running in 64-bit mode.
@N: MF667 |Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.)
@N: MO231 :"d:\02_lscc\09_gsr\final\lab02_prop_circuit_arst\imp1\reveal_workspace\tmpreveal\cnt_uniq_3.vhd":51:8:51:9|Found counter in view:work.Top(behave) instance CNT04.Couti[15:0] 
@N: MO231 :"d:\02_lscc\09_gsr\final\lab02_prop_circuit_arst\imp1\reveal_workspace\tmpreveal\cnt_uniq_2.vhd":51:8:51:9|Found counter in view:work.Top(behave) instance CNT03.Couti[15:0] 
@N: MO231 :"d:\02_lscc\09_gsr\final\lab02_prop_circuit_arst\imp1\reveal_workspace\tmpreveal\cnt_uniq_1.vhd":51:8:51:9|Found counter in view:work.Top(behave) instance CNT02.Couti[15:0] 
@N: MO231 :"d:\02_lscc\09_gsr\final\lab02_prop_circuit_arst\imp1\reveal_workspace\tmpreveal\cnt_uniq_0.vhd":51:8:51:9|Found counter in view:work.Top(behave) instance CNT01.Couti[15:0] 
@N: MF794 |RAM event_cntr_reg_1[2:0] required 3 registers during mapping 
@N: MF794 |RAM genblk1\.te_tt_dist_ram.mem[7:0] required 24 registers during mapping 
@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  
@N: BW103 |The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns.
@N: BW107 |Synopsys Constraint File capacitance units using default value of 1pF 
@N: MT615 |Found clock rvltck with period 33.33ns 
@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
