# Reading pref.tcl
# do D:/02_LSCC/09_GSR/Final/LAB02_Prop_Circuit_ARST/Sim001/Sim001.mdo
# Loading project Sim001
# Compile of CNT.vhd was successful.
# Compile of MyPackage.vhd was successful.
# Compile of Top.vhd was successful.
# Compile of CE_Sync.vhd was successful.
# Compile of LAB03_GSR_LSR_tb.vhd was successful.
# 5 compiles, 0 failed with no errors.
# vsim -voptargs="+acc" -lib work -L pmi_work -L ovi_lfcpnx -suppress vsim-7033,vsim-8630,3009,3389 testbench 
# Start time: 09:21:04 on Nov 29,2023
# //  ModelSim - Lattice FPGA Edition 2021.4 Oct 14 2021
# //
# //  Copyright 1991-2021 Mentor Graphics Corporation
# //  All Rights Reserved.
# //
# //  ModelSim - Lattice FPGA Edition and its associated documentation contain trade
# //  secrets and commercial or financial information that are the property of
# //  Mentor Graphics Corporation and are privileged, confidential,
# //  and exempt from disclosure under the Freedom of Information Act,
# //  5 U.S.C. Section 552. Furthermore, this information
# //  is prohibited from disclosure under the Trade Secrets Act,
# //  18 U.S.C. Section 1905.
# //
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading ieee.numeric_std(body)
# Loading work.testbench(behavior)
# Loading ieee.std_logic_arith(body)
# Loading ieee.std_logic_signed(body)
# Loading ieee.std_logic_unsigned(body)
# Loading work.mysettings
# Loading work.top(behave)
# Loading work.ce_sync(rtl)
# Loading ovi_lfcpnx.DCC
# Loading ovi_lfcpnx.dcc_hw
# Loading sv_std.std
# Loading ovi_lfcpnx.OSCA
# Loading ovi_lfcpnx.OSC_CORE
# Loading ovi_lfcpnx.osc_jedi
# Loading ovi_lfcpnx.osc_digital
# Loading ovi_lfcpnx.stop
# Loading ovi_lfcpnx.osc_analog
# Loading ovi_lfcpnx.VHI
# Loading ovi_lfcpnx.VLO
# Loading work.cnt(rtl)
# .main_pane.wave.interior.cs.body.pw.wf
add wave -position end  sim:/testbench/uut/CLK1
add wave -position end  sim:/testbench/uut/CLK
add wave -position end  sim:/testbench/uut/rsti
add wave -position end sim:/testbench/uut/CE001/*
restart
# ** Note: (vsim-12125) Error and warning message counts have been reset to '0' because of 'restart'.
run
# End time: 07:15:04 on Nov 30,2023, Elapsed time: 21:54:00
# Errors: 0, Warnings: 1
