Synthesis Report
synthesis:  version Radiant Software (64-bit) 2023.1.1.200.1

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2023 Lattice Semiconductor Corporation,  All rights reserved.
Mon Nov 20 10:33:26 2023


Command Line:  C:\lscc\radiant\2023.1\ispfpga\bin\nt64\synthesis.exe -f LAB06_impl_1_lattice.synproj -gui -msgset D:/02_LSCC/09_GSR/Final/LAB06_Mem_rst/promote.xml 

Synthesis options:
The -a option is LFCPNX.
The -t option is ASG256.
The -sp option is 9_High-Performance_1.0V.
The -p option is LFCPNX-100.
                                                          


##########################################################


### Lattice Family     : LFCPNX


### Device             : LFCPNX-100


### Package            : ASG256


### Performance Grade  : 9_High-Performance_1.0V


                                                         


INFO <35001786> - synthesis: User-Selected Strategy Settings
Optimization goal = Timing
Top-level module name = DPRAM1.
Target frequency = 200.000000 MHz.
Maximum fanout = 1000.
Timing path count = 3 (default)
BRAM utilization = 100.000000 %
DSP usage = true
DSP utilization = 100.000000 %
fsm_encoding_style = auto
resolve_mixed_drivers = 0
fix_gated_clocks = 1


Mux style = auto (Default)
Use Carry Chain = true
carry_chain_length = 0
Loop Limit = 1950.
Use IO Insertion = TRUE
Use IO Reg = AUTO

Resource Sharing = TRUE
Propagate Constants = TRUE
Remove Duplicate Registers = TRUE
force_gsr = yes
Output HDL file name = LAB06_impl_1.vm.
ROM style = auto
RAM style = auto
The -comp option is FALSE.
The -syn option is FALSE.
Hardtimer checking is enabled (default). The -dt option is not used.
-path C:/lscc/radiant/2023.1/ispfpga/jd5d00/data (searchpath added)
-path D:/02_LSCC/09_GSR/Final/LAB06_Mem_rst (searchpath added)
-path D:/02_LSCC/09_GSR/Final/LAB06_Mem_rst/impl_1 (searchpath added)
Mixed language design
Verilog design file = C:/lscc/radiant/2023.1/ip/pmi/pmi_lfcpnx.v
VHDL library = pmi
VHDL design file = C:/lscc/radiant/2023.1/ip/pmi/pmi_lfcpnx.vhd
VHDL library = work
VHDL design file = D:/02_LSCC/09_GSR/Final/LAB06_Mem_rst/source/impl_1/Top.vhd
VHDL library = work
VHDL design file = D:/02_LSCC/09_GSR/Final/LAB06_Mem_rst/source/impl_1/MyPackage.vhd
The -r option is OFF. [ Remove LOC Properties is OFF. ]
WARNING <35935050> - synthesis: input port MBISTCLK is not connected on this instance. VDB-5050
Compile design.
Compile Design Begin
Analyzing Verilog file c:/lscc/radiant/2023.1/ip/pmi/pmi_lfcpnx.v. VERI-1482
INFO <35901328> - synthesis: c:/lscc/radiant/2023.1/ip/pmi/pmi_lfcpnx.v(1): analyzing included file c:/lscc/radiant/2023.1/ip/pmi/pmi_addsub.v. VERI-1328
INFO <35901328> - synthesis: c:/lscc/radiant/2023.1/ip/pmi/pmi_addsub.v(40): analyzing included file c:/lscc/radiant/2023.1/ip/pmi/../common/adder_subtractor/rtl/lscc_add_sub.v. VERI-1328
INFO <35901328> - synthesis: c:/lscc/radiant/2023.1/ip/pmi/pmi_lfcpnx.v(2): analyzing included file c:/lscc/radiant/2023.1/ip/pmi/pmi_add.v. VERI-1328
INFO <35901328> - synthesis: c:/lscc/radiant/2023.1/ip/pmi/pmi_add.v(50): analyzing included file c:/lscc/radiant/2023.1/ip/pmi/../common/adder/rtl/lscc_adder.v. VERI-1328
INFO <35901328> - synthesis: c:/lscc/radiant/2023.1/ip/pmi/pmi_lfcpnx.v(3): analyzing included file c:/lscc/radiant/2023.1/ip/pmi/pmi_complex_mult.v. VERI-1328
INFO <35901328> - synthesis: c:/lscc/radiant/2023.1/ip/pmi/pmi_complex_mult.v(52): analyzing included file c:/lscc/radiant/2023.1/ip/pmi/../common/complex_mult/rtl/lscc_complex_mult.v. VERI-1328
INFO <35901328> - synthesis: c:/lscc/radiant/2023.1/ip/pmi/pmi_lfcpnx.v(4): analyzing included file c:/lscc/radiant/2023.1/ip/pmi/pmi_counter.v. VERI-1328
INFO <35901328> - synthesis: c:/lscc/radiant/2023.1/ip/pmi/pmi_counter.v(39): analyzing included file c:/lscc/radiant/2023.1/ip/pmi/../common/counter/rtl/lscc_cntr.v. VERI-1328
INFO <35901328> - synthesis: c:/lscc/radiant/2023.1/ip/pmi/pmi_lfcpnx.v(5): analyzing included file c:/lscc/radiant/2023.1/ip/pmi/pmi_distributed_dpram.v. VERI-1328
INFO <35901328> - synthesis: c:/lscc/radiant/2023.1/ip/pmi/pmi_distributed_dpram.v(43): analyzing included file c:/lscc/radiant/2023.1/ip/pmi/../common/distributed_dpram/rtl/lscc_distributed_dpram.v. VERI-1328
INFO <35901328> - synthesis: c:/lscc/radiant/2023.1/ip/pmi/pmi_lfcpnx.v(6): analyzing included file c:/lscc/radiant/2023.1/ip/pmi/pmi_distributed_spram.v. VERI-1328
INFO <35901328> - synthesis: c:/lscc/radiant/2023.1/ip/pmi/pmi_distributed_spram.v(42): analyzing included file c:/lscc/radiant/2023.1/ip/pmi/../common/distributed_spram/rtl/lscc_distributed_spram.v. VERI-1328
INFO <35901328> - synthesis: c:/lscc/radiant/2023.1/ip/pmi/pmi_lfcpnx.v(7): analyzing included file c:/lscc/radiant/2023.1/ip/pmi/pmi_distributed_rom.v. VERI-1328
INFO <35901328> - synthesis: c:/lscc/radiant/2023.1/ip/pmi/pmi_distributed_rom.v(42): analyzing included file c:/lscc/radiant/2023.1/ip/pmi/../common/distributed_rom/rtl/lscc_distributed_rom.v. VERI-1328
INFO <35901328> - synthesis: c:/lscc/radiant/2023.1/ip/pmi/pmi_lfcpnx.v(8): analyzing included file c:/lscc/radiant/2023.1/ip/pmi/pmi_distributed_shift_reg.v. VERI-1328
INFO <35901328> - synthesis: c:/lscc/radiant/2023.1/ip/pmi/pmi_distributed_shift_reg.v(41): analyzing included file c:/lscc/radiant/2023.1/ip/pmi/../common/ram_shift_reg/rtl/lscc_shift_register.v. VERI-1328
INFO <35901328> - synthesis: c:/lscc/radiant/2023.1/ip/pmi/pmi_lfcpnx.v(9): analyzing included file c:/lscc/radiant/2023.1/ip/pmi/pmi_fifo.v. VERI-1328
INFO <35901328> - synthesis: c:/lscc/radiant/2023.1/ip/pmi/pmi_fifo.v(44): analyzing included file c:/lscc/radiant/2023.1/ip/pmi/../avant/fifo/rtl/lscc_fifo.v. VERI-1328
INFO <35901328> - synthesis: c:/lscc/radiant/2023.1/ip/pmi/pmi_lfcpnx.v(10): analyzing included file c:/lscc/radiant/2023.1/ip/pmi/pmi_fifo_dc.v. VERI-1328
INFO <35901328> - synthesis: c:/lscc/radiant/2023.1/ip/pmi/pmi_fifo_dc.v(47): analyzing included file c:/lscc/radiant/2023.1/ip/pmi/../avant/fifo_dc/rtl/lscc_fifo_dc.v. VERI-1328
INFO <35901328> - synthesis: c:/lscc/radiant/2023.1/ip/pmi/pmi_lfcpnx.v(11): analyzing included file c:/lscc/radiant/2023.1/ip/pmi/pmi_mac.v. VERI-1328
INFO <35901328> - synthesis: c:/lscc/radiant/2023.1/ip/pmi/pmi_mac.v(52): analyzing included file c:/lscc/radiant/2023.1/ip/pmi/../common/mult_accumulate/rtl/lscc_mult_accumulate.v. VERI-1328
INFO <35901328> - synthesis: c:/lscc/radiant/2023.1/ip/pmi/pmi_lfcpnx.v(12): analyzing included file c:/lscc/radiant/2023.1/ip/pmi/pmi_multaddsubsum.v. VERI-1328
INFO <35901328> - synthesis: c:/lscc/radiant/2023.1/ip/pmi/pmi_multaddsubsum.v(53): analyzing included file c:/lscc/radiant/2023.1/ip/pmi/../common/mult_add_sub_sum/rtl/lscc_mult_add_sub_sum.v. VERI-1328
INFO <35901328> - synthesis: c:/lscc/radiant/2023.1/ip/pmi/pmi_lfcpnx.v(13): analyzing included file c:/lscc/radiant/2023.1/ip/pmi/pmi_multaddsub.v. VERI-1328
INFO <35901328> - synthesis: c:/lscc/radiant/2023.1/ip/pmi/pmi_multaddsub.v(52): analyzing included file c:/lscc/radiant/2023.1/ip/pmi/../common/mult_add_sub/rtl/lscc_mult_add_sub.v. VERI-1328
INFO <35901328> - synthesis: c:/lscc/radiant/2023.1/ip/pmi/pmi_lfcpnx.v(14): analyzing included file c:/lscc/radiant/2023.1/ip/pmi/pmi_mult.v. VERI-1328
INFO <35901328> - synthesis: c:/lscc/radiant/2023.1/ip/pmi/pmi_mult.v(51): analyzing included file c:/lscc/radiant/2023.1/ip/pmi/../common/multiplier/rtl/lscc_multiplier.v. VERI-1328
INFO <35901328> - synthesis: c:/lscc/radiant/2023.1/ip/pmi/pmi_lfcpnx.v(15): analyzing included file c:/lscc/radiant/2023.1/ip/pmi/pmi_ram_dp.v. VERI-1328
INFO <35901328> - synthesis: c:/lscc/radiant/2023.1/ip/pmi/pmi_ram_dp.v(48): analyzing included file c:/lscc/radiant/2023.1/ip/pmi/../avant/ram_dp/rtl/lscc_ram_dp.v. VERI-1328
INFO <35901328> - synthesis: c:/lscc/radiant/2023.1/ip/pmi/pmi_lfcpnx.v(16): analyzing included file c:/lscc/radiant/2023.1/ip/pmi/pmi_ram_dp_be.v. VERI-1328
INFO <35901328> - synthesis: c:/lscc/radiant/2023.1/ip/pmi/pmi_ram_dp_be.v(49): analyzing included file c:/lscc/radiant/2023.1/ip/pmi/../avant/ram_dp/rtl/lscc_ram_dp.v. VERI-1328
INFO <35901328> - synthesis: c:/lscc/radiant/2023.1/ip/pmi/pmi_lfcpnx.v(17): analyzing included file c:/lscc/radiant/2023.1/ip/pmi/pmi_ram_dp_true.v. VERI-1328
INFO <35901328> - synthesis: c:/lscc/radiant/2023.1/ip/pmi/pmi_ram_dp_true.v(49): analyzing included file c:/lscc/radiant/2023.1/ip/pmi/../avant/ram_dp_true/rtl/lscc_ram_dp_true.v. VERI-1328
INFO <35901328> - synthesis: c:/lscc/radiant/2023.1/ip/pmi/pmi_lfcpnx.v(18): analyzing included file c:/lscc/radiant/2023.1/ip/pmi/pmi_ram_dq.v. VERI-1328
INFO <35901328> - synthesis: c:/lscc/radiant/2023.1/ip/pmi/pmi_ram_dq.v(45): analyzing included file c:/lscc/radiant/2023.1/ip/pmi/../avant/ram_dq/rtl/lscc_ram_dq.v. VERI-1328
INFO <35901328> - synthesis: c:/lscc/radiant/2023.1/ip/pmi/pmi_lfcpnx.v(19): analyzing included file c:/lscc/radiant/2023.1/ip/pmi/pmi_ram_dq_be.v. VERI-1328
INFO <35901328> - synthesis: c:/lscc/radiant/2023.1/ip/pmi/pmi_ram_dq_be.v(45): analyzing included file c:/lscc/radiant/2023.1/ip/pmi/../avant/ram_dq/rtl/lscc_ram_dq.v. VERI-1328
INFO <35901328> - synthesis: c:/lscc/radiant/2023.1/ip/pmi/pmi_lfcpnx.v(20): analyzing included file c:/lscc/radiant/2023.1/ip/pmi/pmi_rom.v. VERI-1328
INFO <35901328> - synthesis: c:/lscc/radiant/2023.1/ip/pmi/pmi_rom.v(45): analyzing included file c:/lscc/radiant/2023.1/ip/pmi/../avant/rom/rtl/lscc_rom.v. VERI-1328
INFO <35901328> - synthesis: c:/lscc/radiant/2023.1/ip/pmi/pmi_lfcpnx.v(21): analyzing included file c:/lscc/radiant/2023.1/ip/pmi/pmi_sub.v. VERI-1328
INFO <35901328> - synthesis: c:/lscc/radiant/2023.1/ip/pmi/pmi_sub.v(50): analyzing included file c:/lscc/radiant/2023.1/ip/pmi/../common/subtractor/rtl/lscc_subtractor.v. VERI-1328
Analyzing VHDL file c:/lscc/radiant/2023.1/ip/pmi/pmi_lfcpnx.vhd. VHDL-1481
Analyzing VHDL file c:/lscc/radiant/2023.1/ip/pmi/pmi_lfcpnx.vhd

INFO <35921014> - synthesis: c:/lscc/radiant/2023.1/ip/pmi/pmi_lfcpnx.vhd(4): analyzing package components. VHDL-1014
Analyzing VHDL file d:/02_lscc/09_gsr/final/lab06_mem_rst/source/impl_1/mypackage.vhd. VHDL-1481
Analyzing VHDL file d:/02_lscc/09_gsr/final/lab06_mem_rst/source/impl_1/mypackage.vhd

INFO <35921014> - synthesis: d:/02_lscc/09_gsr/final/lab06_mem_rst/source/impl_1/mypackage.vhd(5): analyzing package mysettings. VHDL-1014
Analyzing VHDL file d:/02_lscc/09_gsr/final/lab06_mem_rst/source/impl_1/top.vhd. VHDL-1481
Analyzing VHDL file d:/02_lscc/09_gsr/final/lab06_mem_rst/source/impl_1/top.vhd

INFO <35921012> - synthesis: d:/02_lscc/09_gsr/final/lab06_mem_rst/source/impl_1/top.vhd(6): analyzing entity dpram1. VHDL-1012
INFO <35921010> - synthesis: d:/02_lscc/09_gsr/final/lab06_mem_rst/source/impl_1/top.vhd(19): analyzing architecture rtl. VHDL-1010
INFO <35921504> - synthesis: The default VHDL library search path is now "D:/02_LSCC/09_GSR/Final/LAB06_Mem_rst/impl_1". VHDL-1504
Top module language type = VHDL.
Top module name (VHDL, mixed language): DPRAM1
                                                         


### Number of Logic Cells: 79872


### Number of RAM Blocks: 208


### Number of DSP Blocks: 1287


### Number of PLLs: 4


### Number of IO Pins: 299


##########################################################


                                                         





GSR instance connected to net n119031.
Applying 200.000000 MHz constraint to all clocks

Starting design annotation....
WARNING <70009502> - synthesis: The preferred point for defining clocks is top level ports and driver pins. Pad delays will not be taken into consideration if clocks are defined on nets.
WARNING <70009502> - synthesis: The preferred point for defining clocks is top level ports and driver pins. Pad delays will not be taken into consideration if clocks are defined on nets.

Starting full timing analysis...
Starting design annotation....
WARNING <70009502> - synthesis: The preferred point for defining clocks is top level ports and driver pins. Pad delays will not be taken into consideration if clocks are defined on nets.
WARNING <70009502> - synthesis: The preferred point for defining clocks is top level ports and driver pins. Pad delays will not be taken into consideration if clocks are defined on nets.

Starting full timing analysis...
Starting design annotation....
WARNING <70009502> - synthesis: The preferred point for defining clocks is top level ports and driver pins. Pad delays will not be taken into consideration if clocks are defined on nets.
WARNING <70009502> - synthesis: The preferred point for defining clocks is top level ports and driver pins. Pad delays will not be taken into consideration if clocks are defined on nets.

Starting full timing analysis...
Starting design annotation....
WARNING <70009502> - synthesis: The preferred point for defining clocks is top level ports and driver pins. Pad delays will not be taken into consideration if clocks are defined on nets.
WARNING <70009502> - synthesis: The preferred point for defining clocks is top level ports and driver pins. Pad delays will not be taken into consideration if clocks are defined on nets.

Starting full timing analysis...
INFO <35001701> - synthesis: Net wr_data_i_c_0 with fanout 1024 was buffered for fixing max_fanout violation.
INFO <35001701> - synthesis: Net wr_data_i_c_0 with fanout 1024 was buffered for fixing max_fanout violation.
INFO <35001701> - synthesis: Net wr_data_i_c_1 with fanout 1024 was buffered for fixing max_fanout violation.
INFO <35001701> - synthesis: Net wr_data_i_c_1 with fanout 1024 was buffered for fixing max_fanout violation.
INFO <35001701> - synthesis: Net wr_data_i_c_2 with fanout 1024 was buffered for fixing max_fanout violation.
INFO <35001701> - synthesis: Net wr_data_i_c_2 with fanout 1024 was buffered for fixing max_fanout violation.
INFO <35001701> - synthesis: Net wr_data_i_c_3 with fanout 1024 was buffered for fixing max_fanout violation.
INFO <35001701> - synthesis: Net wr_data_i_c_3 with fanout 1024 was buffered for fixing max_fanout violation.
INFO <35001701> - synthesis: Net wr_data_i_c_4 with fanout 1024 was buffered for fixing max_fanout violation.
INFO <35001701> - synthesis: Net wr_data_i_c_4 with fanout 1024 was buffered for fixing max_fanout violation.
INFO <35001701> - synthesis: Net wr_data_i_c_5 with fanout 1024 was buffered for fixing max_fanout violation.
INFO <35001701> - synthesis: Net wr_data_i_c_5 with fanout 1024 was buffered for fixing max_fanout violation.
INFO <35001701> - synthesis: Net wr_data_i_c_6 with fanout 1024 was buffered for fixing max_fanout violation.
INFO <35001701> - synthesis: Net wr_data_i_c_6 with fanout 1024 was buffered for fixing max_fanout violation.
INFO <35001701> - synthesis: Net wr_data_i_c_7 with fanout 1024 was buffered for fixing max_fanout violation.
INFO <35001701> - synthesis: Net wr_data_i_c_7 with fanout 1024 was buffered for fixing max_fanout violation.
INFO <35001701> - synthesis: Net wr_data_i_c_8 with fanout 1024 was buffered for fixing max_fanout violation.
INFO <35001701> - synthesis: Net wr_data_i_c_8 with fanout 1024 was buffered for fixing max_fanout violation.
INFO <35001701> - synthesis: Net wr_data_i_c_9 with fanout 1024 was buffered for fixing max_fanout violation.
INFO <35001701> - synthesis: Net wr_data_i_c_9 with fanout 1024 was buffered for fixing max_fanout violation.
INFO <35001701> - synthesis: Net wr_data_i_c_10 with fanout 1024 was buffered for fixing max_fanout violation.
INFO <35001701> - synthesis: Net wr_data_i_c_10 with fanout 1024 was buffered for fixing max_fanout violation.
INFO <35001701> - synthesis: Net wr_data_i_c_11 with fanout 1024 was buffered for fixing max_fanout violation.
INFO <35001701> - synthesis: Net wr_data_i_c_11 with fanout 1024 was buffered for fixing max_fanout violation.
INFO <35001701> - synthesis: Net wr_data_i_c_12 with fanout 1024 was buffered for fixing max_fanout violation.
INFO <35001701> - synthesis: Net wr_data_i_c_12 with fanout 1024 was buffered for fixing max_fanout violation.
INFO <35001701> - synthesis: Net wr_data_i_c_13 with fanout 1024 was buffered for fixing max_fanout violation.
INFO <35001701> - synthesis: Net wr_data_i_c_13 with fanout 1024 was buffered for fixing max_fanout violation.
INFO <35001701> - synthesis: Net wr_data_i_c_14 with fanout 1024 was buffered for fixing max_fanout violation.
INFO <35001701> - synthesis: Net wr_data_i_c_14 with fanout 1024 was buffered for fixing max_fanout violation.
INFO <35001701> - synthesis: Net wr_data_i_c_15 with fanout 1024 was buffered for fixing max_fanout violation.
INFO <35001701> - synthesis: Net wr_data_i_c_15 with fanout 1024 was buffered for fixing max_fanout violation.
INFO <35001701> - synthesis: Net wr_data_i_c_16 with fanout 1024 was buffered for fixing max_fanout violation.
INFO <35001701> - synthesis: Net wr_data_i_c_16 with fanout 1024 was buffered for fixing max_fanout violation.
INFO <35001701> - synthesis: Net wr_data_i_c_17 with fanout 1024 was buffered for fixing max_fanout violation.
INFO <35001701> - synthesis: Net wr_data_i_c_17 with fanout 1024 was buffered for fixing max_fanout violation.
INFO <35001701> - synthesis: Net rd_addr_i_c_0 with fanout 9216 was buffered for fixing max_fanout violation.
INFO <35001701> - synthesis: Net rd_addr_i_c_0 with fanout 9216 was buffered for fixing max_fanout violation.
INFO <35001701> - synthesis: Net rd_addr_i_c_0 with fanout 9216 was buffered for fixing max_fanout violation.
INFO <35001701> - synthesis: Net rd_addr_i_c_0 with fanout 9216 was buffered for fixing max_fanout violation.
INFO <35001701> - synthesis: Net rd_addr_i_c_0 with fanout 9216 was buffered for fixing max_fanout violation.
INFO <35001701> - synthesis: Net rd_addr_i_c_0 with fanout 9216 was buffered for fixing max_fanout violation.
INFO <35001701> - synthesis: Net rd_addr_i_c_0 with fanout 9216 was buffered for fixing max_fanout violation.
INFO <35001701> - synthesis: Net rd_addr_i_c_0 with fanout 9216 was buffered for fixing max_fanout violation.
INFO <35001701> - synthesis: Net rd_addr_i_c_0 with fanout 9216 was buffered for fixing max_fanout violation.
INFO <35001701> - synthesis: Net rd_addr_i_c_0 with fanout 9216 was buffered for fixing max_fanout violation.
INFO <35001701> - synthesis: Net rd_addr_i_c_1 with fanout 4608 was buffered for fixing max_fanout violation.
INFO <35001701> - synthesis: Net rd_addr_i_c_1 with fanout 4608 was buffered for fixing max_fanout violation.
INFO <35001701> - synthesis: Net rd_addr_i_c_1 with fanout 4608 was buffered for fixing max_fanout violation.
INFO <35001701> - synthesis: Net rd_addr_i_c_1 with fanout 4608 was buffered for fixing max_fanout violation.
INFO <35001701> - synthesis: Net rd_addr_i_c_1 with fanout 4608 was buffered for fixing max_fanout violation.
INFO <35001701> - synthesis: Net rd_addr_i_c_2 with fanout 2304 was buffered for fixing max_fanout violation.
INFO <35001701> - synthesis: Net rd_addr_i_c_2 with fanout 2304 was buffered for fixing max_fanout violation.
INFO <35001701> - synthesis: Net rd_addr_i_c_2 with fanout 2304 was buffered for fixing max_fanout violation.
INFO <35001701> - synthesis: Net rd_addr_i_c_3 with fanout 1152 was buffered for fixing max_fanout violation.
INFO <35001701> - synthesis: Net rd_addr_i_c_3 with fanout 1152 was buffered for fixing max_fanout violation.
WARNING <35935047> - synthesis: Unused instance GSR_INST is removed. VDB-5047


Area Report

################### Begin Area Report (DPRAM1)######################
Number of register bits => 18450 of 79872 (23 % )
FD1P3BX => 18
FD1P3DX => 18432
GSR => 1
IB => 45
LUT4 => 1146
OB => 18
WIDEFN9 => 6138
################### End Area Report ##################
Number of odd-length carry chains : 0
Number of even-length carry chains : 0


Clock Report

################### Begin Clock Report ######################
Clock Nets
Number of Clocks: 2
  Net : wr_clk_i_c, loads : 18432
  Net : rd_clk_i_c, loads : 18
Clock Enable Nets
Number of Clock Enables: 1025
Top 10 highest fanout Clock Enables:
  Net : wr_clk_i_c_enable_7944, loads : 18
  Net : wr_clk_i_c_enable_18417, loads : 18
  Net : wr_clk_i_c_enable_7916, loads : 18
  Net : wr_clk_i_c_enable_2475, loads : 18
  Net : wr_clk_i_c_enable_7893, loads : 18
  Net : wr_clk_i_c_enable_2473, loads : 18
  Net : wr_clk_i_c_enable_7867, loads : 18
  Net : wr_clk_i_c_enable_2471, loads : 18
  Net : wr_clk_i_c_enable_7845, loads : 18
  Net : wr_clk_i_c_enable_2470, loads : 18
Highest fanout non-clock nets
Top 10 highest fanout non-clock nets:
  Net : n153051, loads : 1000
  Net : n153049, loads : 1000
  Net : n153048, loads : 1000
  Net : n153046, loads : 1000
  Net : n153045, loads : 1000
  Net : n153044, loads : 1000
  Net : n153043, loads : 1000
  Net : n153041, loads : 1000
  Net : n153040, loads : 1000
  Net : n153039, loads : 1000
################### End Clock Report ##################

Peak Memory Usage: 576 MB

--------------------------------------------------------------
Total CPU Time: 9 secs 
Total REAL Time: 1 mins 29 secs 
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