Lattice Mapping Report File
Design:  Top
Family:  LFCPNX
Device:  LFCPNX-100
Package: LFG672
Performance Grade:  9_High-Performance_1.0V

Mapper:    version Radiant Software (64-bit) 2023.1.1.200.1
Mapped on: Mon Oct  9 09:48:12 2023


Design Information

Command line:   map -i LAB01_Async_rst_syn.udb -pdc
     D:/02_LSCC/09_GSR/Final/LAB01_Async_rst/Myconstraints.pdc -o
     LAB01_Async_rst_map.udb -mp LAB01_Async_rst.mrp -hierrpt -gui

Design Summary
   Number of registers:         994 out of 80769 (1%)
      Number of SLICE         registers:  990 out of 79872 (1%)
      Number of PIO Input     registers:    0 out of   299 (0%)
      Number of PIO Output    registers:    4 out of   299 (1%)
      Number of PIO Tri-State registers:    0 out of   299 (0%)
   Number of LUT4s:            1343 out of 79872 (2%)
      Number used as logic LUT4s:                       1015
      Number used as distributed RAM:                     36 (6 per 16X4 RAM)
      Number used as ripple logic:                       292 (2 per CCU2)
   Number of PIOs used/reserved:   13 out of   299 (4%)
      Number of PIOs reserved:      3 (per sysConfig and/or prohibit constraint)
      Number of PIOs used:         10
        Number of PIOs used for single ended IO:        10
        Number of PIO pairs used for differential IO:    0
        Number allocated to regular speed PIOs:     9 out of  167 (5%)
        Number allocated to high speed PIOs:        1 out of  132 (1%)
   Number of Dedicated IO used for ADC/PCS/PCIE:    0 out of   60 (0%)
   Number of IDDR/ODDR/TDDR functions used:      0 out of   730 (0%)
   Number of IOs using at least one DDR function: 0 (0 differential)
   Number of Block RAMs:          2 out of 208 (0%)
   Number of Large RAMs:          0 out of 7 (0%)
   Number of Logical DSP Functions:
      Number of Pre-Adders (9+9):    0 out of 312 (0%)
      Number of Multipliers (18x18): 0 out of 156 (0%)
         Number of 9X9:        0 (1 18x18 = 2   9x9)
         Number of 18x18:      0 (1 18x18 = 1 18x18)
         Number of 18x36:      0 (2 18x18 = 1 18x36)
         Number of 36x36:      0 (4 18x18 = 1 36x36)
      Number of 54-bit Accumulators: 0 out of 78 (0%)
      Number of 18-bit Registers:    0 out of 312 (0%)
   Number of Physical DSP Components:
      Number of PREADD9:             0 out of 312 (0%)
      Number of MULT9:               0 out of 312 (0%)
      Number of MULT18:              0 out of 156 (0%)
      Number of MULT18X36:           0 out of 78 (0%)
      Number of MULT36:              0 out of 39 (0%)
      Number of ACC54:               0 out of 78 (0%)
      Number of REG18:               0 out of 312 (0%)
   Number of ALUREGs:             0 out of 1 (0%)
   Number of PLLs:                0 out of 4 (0%)
   Number of DDRDLLs:             0 out of 2 (0%)

   Number of DLLDELs:             0 out of 10 (0%)
   Number of DQSs:                0 out of 11 (0%)
   Number of DCSs:                0 out of 2 (0%)
   Number of DCCs:                0 out of 62 (0%)
   Number of PCLKDIVs:            0 out of 2 (0%)
   Number of ECLKDIVs:            0 out of 12 (0%)
   Number of ECLKSYNCs:           0 out of 12 (0%)
   Number of ADC Blocks:          0 out of 1 (0%)
   Number of SGMIICDRs:           0 out of 2 (0%)
   Number of PMUs:                0 out of 1 (0%)
   Number of BNKREF18s:           0 out of 3 (0%)
   Number of BNKREF33s:           0 out of 5 (0%)
   Number of I2CFIFOs:            0 out of 1 (0%)
   Number of Oscillators:         1 out of 1 (100%)
   Number of GSR:                 1 out of 1 (100%)
   Number of Cryptographic Block: 0 out of 1 (0%)
   Number of Config IP:           0 out of 1 (0%)
                 TSALL:           0 out of 1 (0%)
   Number of JTAG:                1 out of 1 (100%)
   Number of SED:                 0 out of 1 (0%)
   Number of PCSs:                0 out of 2 (0%)
   Number of PCIE Link Layers:    0 out of 1 (0%)
   Number of Clocks:  3
      Net jtck: 409 loads, 0 rising, 409 falling (Driver: Pin
     jtaghub_inst.jtagg_u/JTCK)
      Net jtaghub_inst.tck: 1 loads, 1 rising, 0 falling (Driver: Port TCK)
      Net clk150: 529 loads, 529 rising, 0 falling (Driver: Pin
     OSCA001.OSCA_inst/HFCLKOUT)
   Number of Clock Enables:  69
      Net VCC: 2 loads, 0 SLICEs
      Net jtaghub_inst.er1_shift_reg8: 23 loads, 23 SLICEs
      Net ip_enable[0]: 37 loads, 37 SLICEs
      Net jtaghub_inst.JUPDATE: 13 loads, 13 SLICEs
      Net secured_signal_142: 11 loads, 11 SLICEs
      Net secured_signal_151: 3 loads, 3 SLICEs
      Net secured_signal_174: 1 loads, 1 SLICEs
      Net secured_signal_175: 1 loads, 1 SLICEs
      Net secured_signal_187: 10 loads, 10 SLICEs
      Net secured_signal_209: 5 loads, 5 SLICEs
      Net secured_signal_211: 2 loads, 2 SLICEs
      Net secured_signal_215: 3 loads, 3 SLICEs
      Net secured_signal_222: 65 loads, 65 SLICEs
      Net secured_signal_224: 3 loads, 3 SLICEs
      Net secured_signal_227: 3 loads, 3 SLICEs
      Net secured_signal_280: 7 loads, 5 SLICEs
      Net secured_signal_298: 5 loads, 5 SLICEs
      Net secured_signal_299: 5 loads, 5 SLICEs
      Net secured_signal_675: 1 loads, 1 SLICEs
      Net secured_signal_718: 2 loads, 2 SLICEs
      Net secured_signal_724: 20 loads, 20 SLICEs
      Net secured_signal_832: 4 loads, 4 SLICEs
      Net secured_signal_849: 16 loads, 16 SLICEs
      Net secured_signal_984: 16 loads, 16 SLICEs
      Net secured_signal_989: 1 loads, 1 SLICEs
      Net secured_signal_1080: 1 loads, 1 SLICEs
      Net secured_signal_1097: 2 loads, 2 SLICEs
      Net secured_signal_1126: 71 loads, 71 SLICEs

      Net secured_signal_1228: 2 loads, 2 SLICEs
      Net secured_signal_1241: 3 loads, 3 SLICEs
      Net secured_signal_1242: 3 loads, 3 SLICEs
      Net secured_signal_1248: 1 loads, 1 SLICEs
      Net secured_signal_1265: 9 loads, 9 SLICEs
      Net secured_signal_1284: 1 loads, 1 SLICEs
      Net secured_signal_1286: 1 loads, 1 SLICEs
      Net secured_signal_1301: 1 loads, 1 SLICEs
      Net secured_signal_1312: 2 loads, 2 SLICEs
      Net secured_signal_1320: 2 loads, 2 SLICEs
      Net secured_signal_1321: 1 loads, 1 SLICEs
      Net secured_signal_1410: 9 loads, 9 SLICEs
      Net secured_signal_1429: 1 loads, 1 SLICEs
      Net secured_signal_1431: 1 loads, 1 SLICEs
      Net secured_signal_1445: 1 loads, 1 SLICEs
      Net secured_signal_1457: 2 loads, 2 SLICEs
      Net secured_signal_1465: 2 loads, 2 SLICEs
      Net secured_signal_1466: 1 loads, 1 SLICEs
      Net secured_signal_1567: 1 loads, 1 SLICEs
      Net secured_signal_1569: 1 loads, 1 SLICEs
      Net secured_signal_1583: 1 loads, 1 SLICEs
      Net secured_signal_1585: 9 loads, 9 SLICEs
      Net secured_signal_1591: 16 loads, 16 SLICEs
      Net secured_signal_1597: 2 loads, 2 SLICEs
      Net secured_signal_1605: 2 loads, 2 SLICEs
      Net secured_signal_1606: 1 loads, 1 SLICEs
      Net secured_signal_1719: 16 loads, 16 SLICEs
      Net secured_signal_1720: 16 loads, 16 SLICEs
      Net secured_signal_1801: 3 loads, 3 SLICEs
      Net secured_signal_1881: 16 loads, 16 SLICEs
      Net secured_signal_1882: 16 loads, 16 SLICEs
      Net secured_signal_1963: 3 loads, 3 SLICEs
      Net secured_signal_2043: 16 loads, 16 SLICEs
      Net secured_signal_2044: 16 loads, 16 SLICEs
      Net secured_signal_2125: 3 loads, 3 SLICEs
      Net secured_signal_2205: 16 loads, 16 SLICEs
      Net secured_signal_2206: 16 loads, 16 SLICEs
      Net secured_signal_2287: 3 loads, 3 SLICEs
      Net secured_signal_2347: 1 loads, 1 SLICEs
      Net secured_signal_2348: 1 loads, 1 SLICEs
      Net secured_signal_2353: 3 loads, 3 SLICEs
   Number of LSRs:  13
      Net VCC: 4 loads, 0 SLICEs
      Pin reset: 36 loads, 36 SLICEs (Net: rsti)
      Net jrstn: 326 loads, 325 SLICEs
      Net secured_signal_1223: 1 loads, 1 SLICEs
      Net secured_signal_1296: 5 loads, 5 SLICEs
      Net secured_signal_1370: 1 loads, 1 SLICEs
      Net secured_signal_1371: 1 loads, 1 SLICEs
      Net secured_signal_1441: 5 loads, 5 SLICEs
      Net secured_signal_1516: 1 loads, 1 SLICEs
      Net secured_signal_1517: 1 loads, 1 SLICEs
      Net secured_signal_1579: 5 loads, 5 SLICEs
      Net secured_signal_1673: 1 loads, 1 SLICEs
      Net secured_signal_1674: 1 loads, 1 SLICEs
   Top 10 highest fanout non-clock nets:
      Net jrstn: 327 loads

      Net top_reveal_coretop_instance.core0.jshift_d1: 106 loads
      Net top_reveal_coretop_instance.core0.addr[4]: 94 loads
      Net top_reveal_coretop_instance.core0.tr_bit_0: 72 loads
      Net secured_signal_1126: 71 loads
      Net secured_signal_222: 65 loads
      Net top_reveal_coretop_instance.core0.addr[0]: 60 loads
      Net top_reveal_coretop_instance.core0.addr[9]: 60 loads
      Net ip_enable[0]: 55 loads
      Net top_reveal_coretop_instance.core0.addr[2]: 51 loads




   Number of warnings:  0
   Number of errors:    0

   Number of warnings:  0
   Number of errors:    0



Design Errors/Warnings

   No errors or warnings present.



IO (PIO) Attributes

+---------------------+-----------+-----------+-------+-------+-----------+
| IO Name             | Direction | Levelmode |  IO   |  IO   | Special   |
|                     |           |  IO_TYPE  |  REG  |  DDR  | IO Buffer |
+---------------------+-----------+-----------+-------+-------+-----------+
| TDI                 | INPUT     |           |       |       |           |
+---------------------+-----------+-----------+-------+-------+-----------+
| TCK                 | INPUT     |           |       |       |           |
+---------------------+-----------+-----------+-------+-------+-----------+
| TMS                 | INPUT     |           |       |       |           |
+---------------------+-----------+-----------+-------+-------+-----------+
| TDO                 | OUTPUT    |           |       |       |           |
+---------------------+-----------+-----------+-------+-------+-----------+
| LED4                | OUTPUT    |           | O     |       |           |
+---------------------+-----------+-----------+-------+-------+-----------+
| LED3                | OUTPUT    |           | O     |       |           |
+---------------------+-----------+-----------+-------+-------+-----------+
| LED2                | OUTPUT    |           | O     |       |           |
+---------------------+-----------+-----------+-------+-------+-----------+
| LED1                | OUTPUT    |           | O     |       |           |
+---------------------+-----------+-----------+-------+-------+-----------+
| en                  | INPUT     |           |       |       |           |
+---------------------+-----------+-----------+-------+-------+-----------+
| reset               | INPUT     |           |       |       |           |
+---------------------+-----------+-----------+-------+-------+-----------+



Removed logic

Block jtaghub_inst/IP_ENABLE_reg[17].ff_inst undriven or does not drive anything
     - clipped.
Block jtaghub_inst/IP_ENABLE_reg[16].ff_inst undriven or does not drive anything
     - clipped.
Block jtaghub_inst/IP_ENABLE_reg[15].ff_inst undriven or does not drive anything

     - clipped.
Block jtaghub_inst/IP_ENABLE_reg[14].ff_inst undriven or does not drive anything
     - clipped.
Block jtaghub_inst/IP_ENABLE_reg[13].ff_inst undriven or does not drive anything
     - clipped.
Block jtaghub_inst/IP_ENABLE_reg[12].ff_inst undriven or does not drive anything
     - clipped.
Block jtaghub_inst/IP_ENABLE_fast_reg[11].ff_inst undriven or does not drive
     anything - clipped.
Block jtaghub_inst/IP_ENABLE_reg[11].ff_inst undriven or does not drive anything
     - clipped.
Block jtaghub_inst/IP_ENABLE_fast_reg[3].ff_inst undriven or does not drive
     anything - clipped.
Block jtaghub_inst/jtdo2_int_m15_N_2L1_cZ undriven or does not drive anything -
     clipped.
Block VCC_cZ was optimized away.
Block jtaghub_inst/jtdo2_int_m15_cZ was optimized away.
Block jtaghub_inst/IP_ENABLE_0_.CN was optimized away.
Block jtaghub_inst/OBZ_inst_RNO was optimized away.
Block jtaghub_inst/jtagg_u_RNI1T52 was optimized away.
Block rsti_RNI2UU was optimized away.
Block jtaghub_inst/jtdo2_int_m11_cZ was optimized away.
Block jtaghub_inst/jtdo2_int_m11_1_cZ was optimized away.
Block jtaghub_inst/jtdo2_int_m8_1_cZ was optimized away.
Block jtaghub_inst/jtdo2_int_m11_1_0_cZ was optimized away.
Block jtaghub_inst/jtdo2_int_m2_cZ was optimized away.
Block jtaghub_inst/jtdo2_int_m2_1_cZ was optimized away.
Block jtaghub_inst/jtagg_u_RNO_2_cZ was optimized away.
Block jtaghub_inst/jtdo2_int_m5_cZ was optimized away.
Block jtaghub_inst/jtdo2_int_m5_1_cZ was optimized away.
Block jtaghub_inst/jtdo2_int_m2_bm_cZ was optimized away.
Block jtaghub_inst/jtdo2_int_m5_bm_cZ was optimized away.

OSC Summary
-----------

OSC 1:                                 Pin/Node Value
  OSC Instance Name:                            OSCA001.OSCA_inst
  Enable High Frequency SDSC:          NODE     VCC
  High Frequency Output:               NODE     clk150
  Low Frequency Output:                         NONE
  SDC Output:                                   NONE
  High Frequency DIV:                           3



ASIC Components
---------------

Instance Name: jtaghub_inst/jtagg_u
         Type: CONFIG_JTAG_CORE
Instance Name: secured_comp_286
         Type: EBR_CORE
Instance Name: secured_comp_287
         Type: EBR_CORE
Instance Name: OSCA001.OSCA_inst
         Type: OSC_CORE





GSR Usage
---------

GSR Component:
   The Global Set Reset (GSR) resource has been used to implement a global reset
        of the design. The reset signal used for GSR control is
        'top_reveal_coretop_instance.core0.reset_rvl_n'.

GSR Property:
   The design components with GSR property set to ENABLED will respond to global
        set reset while the components with GSR property set to DISABLED will
        not.

Components with disabled GSR Property
-------------------------------------

These components have the GSR property set to DISABLED. The components will not
     respond to the reset signal 'top_reveal_coretop_instance.core0.reset_rvl_n'
     via the GSR component.

Type and number of components of the type:
   Register = 449

Type and instance name of component:
   Register : jtaghub_inst.rom_rd_addr_reg[0].ff_inst
   Register : jtaghub_inst.rom_rd_addr_reg[1].ff_inst
   Register : jtaghub_inst.rom_rd_addr_reg[2].ff_inst
   Register : jtaghub_inst.rom_rd_addr_reg[3].ff_inst
   Register : jtaghub_inst.rom_rd_addr_reg[4].ff_inst
   Register : jtaghub_inst.rom_rd_addr_reg[5].ff_inst
   Register : jtaghub_inst.jshift_d1.ff_inst
   Register : jtaghub_inst.jce1_d1_reg.ff_inst
   Register : jtaghub_inst.id_enable_reg.ff_inst
   Register : jtaghub_inst.er1_shift_reg_reg[1].ff_inst
   Register : jtaghub_inst.er1_shift_reg_reg[2].ff_inst
   Register : jtaghub_inst.er1_shift_reg_reg[3].ff_inst
   Register : jtaghub_inst.er1_shift_reg_reg[4].ff_inst
   Register : jtaghub_inst.er1_shift_reg_reg[5].ff_inst
   Register : jtaghub_inst.er1_shift_reg_reg[6].ff_inst
   Register : jtaghub_inst.er1_shift_reg_reg[7].ff_inst
   Register : jtaghub_inst.er1_shift_reg_reg[8].ff_inst
   Register : jtaghub_inst.er1_shift_reg_reg[9].ff_inst
   Register : jtaghub_inst.er1_shift_reg_reg[10].ff_inst
   Register : jtaghub_inst.er1_shift_reg_reg[11].ff_inst
   Register : jtaghub_inst.er1_shift_reg_reg[12].ff_inst
   Register : jtaghub_inst.er1_shift_reg_reg[13].ff_inst
   Register : jtaghub_inst.er1_shift_reg_reg[14].ff_inst
   Register : jtaghub_inst.er1_shift_reg_reg[15].ff_inst
   Register : jtaghub_inst.er1_shift_reg_reg[16].ff_inst
   Register : jtaghub_inst.er1_shift_reg_reg[17].ff_inst
   Register : jtaghub_inst.er1_shift_reg_reg[18].ff_inst
   Register : jtaghub_inst.er1_shift_reg_reg[19].ff_inst
   Register : jtaghub_inst.er1_shift_reg_reg[20].ff_inst
   Register : jtaghub_inst.er1_shift_reg_reg[21].ff_inst
   Register : jtaghub_inst.er1_shift_reg_reg[22].ff_inst
   Register : jtaghub_inst.er1_shift_reg_reg[23].ff_inst
   Register : jtaghub_inst.bit_count_reg[0].ff_inst
   Register : jtaghub_inst.bit_count_reg[1].ff_inst
   Register : jtaghub_inst.bit_count_reg[2].ff_inst
   Register : jtaghub_inst.bit_count_reg[3].ff_inst
   Register : jtaghub_inst.bit_count_reg[4].ff_inst
   Register : jtaghub_inst.IP_ENABLE_reg[0].ff_inst
   Register : jtaghub_inst.IP_ENABLE_reg[1].ff_inst
   Register : jtaghub_inst.IP_ENABLE_reg[2].ff_inst

   Register : jtaghub_inst.IP_ENABLE_reg[3].ff_inst
   Register : jtaghub_inst.IP_ENABLE_reg[4].ff_inst
   Register : jtaghub_inst.IP_ENABLE_reg[5].ff_inst
   Register : jtaghub_inst.IP_ENABLE_reg[6].ff_inst
   Register : jtaghub_inst.IP_ENABLE_reg[7].ff_inst
   Register : jtaghub_inst.IP_ENABLE_fast_reg[8].ff_inst
   Register : jtaghub_inst.IP_ENABLE_reg[8].ff_inst
   Register : jtaghub_inst.IP_ENABLE_reg[9].ff_inst
   Register : jtaghub_inst.IP_ENABLE_reg[10].ff_inst
   Register : secured_comp_298
   Register : secured_comp_299
   Register : secured_comp_300
   Register : secured_comp_301
   Register : secured_comp_302
   Register : secured_comp_303
   Register : secured_comp_304
   Register : secured_comp_305
   Register : secured_comp_306
   Register : secured_comp_307
   Register : secured_comp_308
   Register : secured_comp_309
   Register : secured_comp_310
   Register : secured_comp_311
   Register : secured_comp_312
   Register : secured_comp_313
   Register : secured_comp_314
   Register : secured_comp_315
   Register : secured_comp_316
   Register : secured_comp_317
   Register : secured_comp_318
   Register : secured_comp_319
   Register : secured_comp_320
   Register : secured_comp_321
   Register : secured_comp_322
   Register : secured_comp_323
   Register : secured_comp_324
   Register : secured_comp_325
   Register : secured_comp_326
   Register : secured_comp_327
   Register : secured_comp_328
   Register : secured_comp_329
   Register : secured_comp_330
   Register : secured_comp_331
   Register : secured_comp_332
   Register : secured_comp_333
   Register : secured_comp_334
   Register : secured_comp_335
   Register : secured_comp_336
   Register : secured_comp_337
   Register : secured_comp_338
   Register : secured_comp_339
   Register : secured_comp_340
   Register : secured_comp_341
   Register : secured_comp_342
   Register : secured_comp_343
   Register : secured_comp_344
   Register : secured_comp_345

   Register : secured_comp_346
   Register : secured_comp_347
   Register : secured_comp_348
   Register : secured_comp_349
   Register : secured_comp_350
   Register : secured_comp_351
   Register : secured_comp_352
   Register : secured_comp_353
   Register : secured_comp_354
   Register : secured_comp_355
   Register : secured_comp_356
   Register : secured_comp_357
   Register : secured_comp_358
   Register : secured_comp_359
   Register : secured_comp_360
   Register : secured_comp_361
   Register : secured_comp_362
   Register : secured_comp_433
   Register : secured_comp_434
   Register : secured_comp_435
   Register : secured_comp_436
   Register : secured_comp_437
   Register : secured_comp_438
   Register : secured_comp_439
   Register : secured_comp_440
   Register : secured_comp_801
   Register : secured_comp_802
   Register : secured_comp_803
   Register : secured_comp_804
   Register : secured_comp_805
   Register : secured_comp_806
   Register : secured_comp_807
   Register : secured_comp_808
   Register : secured_comp_809
   Register : secured_comp_810
   Register : secured_comp_811
   Register : secured_comp_812
   Register : secured_comp_813
   Register : secured_comp_814
   Register : secured_comp_815
   Register : secured_comp_816
   Register : secured_comp_817
   Register : secured_comp_818
   Register : secured_comp_819
   Register : secured_comp_820
   Register : secured_comp_821
   Register : secured_comp_822
   Register : secured_comp_823
   Register : secured_comp_824
   Register : secured_comp_825
   Register : secured_comp_826
   Register : secured_comp_827
   Register : secured_comp_828
   Register : secured_comp_829
   Register : secured_comp_830
   Register : secured_comp_831
   Register : secured_comp_832

   Register : secured_comp_833
   Register : secured_comp_834
   Register : secured_comp_835
   Register : secured_comp_836
   Register : secured_comp_837
   Register : secured_comp_838
   Register : secured_comp_839
   Register : secured_comp_840
   Register : secured_comp_841
   Register : secured_comp_842
   Register : secured_comp_843
   Register : secured_comp_844
   Register : secured_comp_845
   Register : secured_comp_846
   Register : secured_comp_847
   Register : secured_comp_848
   Register : secured_comp_849
   Register : secured_comp_850
   Register : secured_comp_851
   Register : secured_comp_852
   Register : secured_comp_853
   Register : secured_comp_854
   Register : secured_comp_855
   Register : secured_comp_856
   Register : secured_comp_857
   Register : secured_comp_858
   Register : secured_comp_859
   Register : secured_comp_860
   Register : secured_comp_861
   Register : secured_comp_862
   Register : secured_comp_863
   Register : secured_comp_864
   Register : secured_comp_865
   Register : secured_comp_866
   Register : secured_comp_867
   Register : secured_comp_868
   Register : secured_comp_869
   Register : secured_comp_870
   Register : secured_comp_871
   Register : secured_comp_872
   Register : secured_comp_873
   Register : secured_comp_874
   Register : secured_comp_875
   Register : secured_comp_876
   Register : secured_comp_877
   Register : secured_comp_878
   Register : secured_comp_879
   Register : secured_comp_880
   Register : secured_comp_881
   Register : secured_comp_882
   Register : secured_comp_883
   Register : secured_comp_884
   Register : secured_comp_885
   Register : secured_comp_886
   Register : secured_comp_887
   Register : secured_comp_888
   Register : secured_comp_889

   Register : secured_comp_890
   Register : secured_comp_891
   Register : secured_comp_892
   Register : secured_comp_893
   Register : secured_comp_894
   Register : secured_comp_895
   Register : secured_comp_896
   Register : secured_comp_897
   Register : secured_comp_898
   Register : secured_comp_899
   Register : secured_comp_900
   Register : secured_comp_901
   Register : secured_comp_902
   Register : secured_comp_903
   Register : secured_comp_904
   Register : secured_comp_905
   Register : secured_comp_906
   Register : secured_comp_907
   Register : secured_comp_908
   Register : secured_comp_909
   Register : secured_comp_910
   Register : secured_comp_911
   Register : secured_comp_912
   Register : secured_comp_913
   Register : secured_comp_914
   Register : secured_comp_915
   Register : secured_comp_916
   Register : secured_comp_917
   Register : secured_comp_918
   Register : secured_comp_919
   Register : secured_comp_920
   Register : secured_comp_921
   Register : secured_comp_922
   Register : secured_comp_923
   Register : secured_comp_924
   Register : secured_comp_925
   Register : secured_comp_926
   Register : secured_comp_927
   Register : secured_comp_928
   Register : secured_comp_929
   Register : secured_comp_930
   Register : secured_comp_931
   Register : secured_comp_932
   Register : secured_comp_933
   Register : secured_comp_934
   Register : secured_comp_935
   Register : secured_comp_936
   Register : secured_comp_937
   Register : secured_comp_938
   Register : secured_comp_939
   Register : secured_comp_940
   Register : secured_comp_941
   Register : secured_comp_942
   Register : secured_comp_943
   Register : secured_comp_944
   Register : secured_comp_945
   Register : secured_comp_946

   Register : secured_comp_947
   Register : secured_comp_948
   Register : secured_comp_949
   Register : secured_comp_950
   Register : secured_comp_951
   Register : secured_comp_956
   Register : secured_comp_957
   Register : secured_comp_958
   Register : secured_comp_959
   Register : secured_comp_960
   Register : secured_comp_961
   Register : secured_comp_962
   Register : secured_comp_963
   Register : secured_comp_964
   Register : secured_comp_965
   Register : secured_comp_966
   Register : secured_comp_967
   Register : secured_comp_972
   Register : secured_comp_973
   Register : secured_comp_974
   Register : secured_comp_975
   Register : secured_comp_976
   Register : secured_comp_977
   Register : secured_comp_978
   Register : secured_comp_979
   Register : secured_comp_980
   Register : secured_comp_981
   Register : secured_comp_982
   Register : secured_comp_983
   Register : secured_comp_984
   Register : secured_comp_1117
   Register : secured_comp_1118
   Register : secured_comp_1123
   Register : secured_comp_1124
   Register : secured_comp_1125
   Register : secured_comp_1128
   Register : secured_comp_1129
   Register : secured_comp_1130
   Register : secured_comp_1131
   Register : secured_comp_1132
   Register : secured_comp_1133
   Register : secured_comp_1134
   Register : secured_comp_1135
   Register : secured_comp_1136
   Register : secured_comp_1137
   Register : secured_comp_1138
   Register : secured_comp_1139
   Register : secured_comp_1140
   Register : secured_comp_1141
   Register : secured_comp_1142
   Register : secured_comp_1143
   Register : secured_comp_1154
   Register : secured_comp_1227
   Register : secured_comp_1228
   Register : secured_comp_1233
   Register : secured_comp_1234
   Register : secured_comp_1235

   Register : secured_comp_1238
   Register : secured_comp_1239
   Register : secured_comp_1240
   Register : secured_comp_1241
   Register : secured_comp_1242
   Register : secured_comp_1243
   Register : secured_comp_1244
   Register : secured_comp_1245
   Register : secured_comp_1246
   Register : secured_comp_1247
   Register : secured_comp_1248
   Register : secured_comp_1249
   Register : secured_comp_1250
   Register : secured_comp_1251
   Register : secured_comp_1252
   Register : secured_comp_1253
   Register : secured_comp_1264
   Register : secured_comp_1340
   Register : secured_comp_1341
   Register : secured_comp_1346
   Register : secured_comp_1347
   Register : secured_comp_1348
   Register : secured_comp_1349
   Register : secured_comp_1352
   Register : secured_comp_1353
   Register : secured_comp_1354
   Register : secured_comp_1355
   Register : secured_comp_1356
   Register : secured_comp_1357
   Register : secured_comp_1358
   Register : secured_comp_1359
   Register : secured_comp_1360
   Register : secured_comp_1361
   Register : secured_comp_1362
   Register : secured_comp_1363
   Register : secured_comp_1364
   Register : secured_comp_1365
   Register : secured_comp_1366
   Register : secured_comp_1367
   Register : secured_comp_1368
   Register : secured_comp_1369
   Register : secured_comp_1370
   Register : secured_comp_1371
   Register : secured_comp_1372
   Register : secured_comp_1373
   Register : secured_comp_1374
   Register : secured_comp_1375
   Register : secured_comp_1376
   Register : secured_comp_1377
   Register : secured_comp_1378
   Register : secured_comp_1379
   Register : secured_comp_1380
   Register : secured_comp_1381
   Register : secured_comp_1382
   Register : secured_comp_1383
   Register : secured_comp_1394
   Register : CNT01.Couti_reg[0].ff_inst

   Register : CNT01.Couti_reg[1].ff_inst
   Register : CNT01.Couti_reg[2].ff_inst
   Register : CNT01.Couti_reg[3].ff_inst
   Register : CNT01.Couti_reg[4].ff_inst
   Register : CNT01.Couti_reg[5].ff_inst
   Register : CNT01.Couti_reg[6].ff_inst
   Register : CNT01.Couti_reg[7].ff_inst
   Register : CNT01.Couti_reg[8].ff_inst
   Register : CNT01.Couti_reg[9].ff_inst
   Register : CNT01.Couti_reg[10].ff_inst
   Register : CNT01.Couti_reg[11].ff_inst
   Register : CNT01.Couti_reg[12].ff_inst
   Register : CNT01.Couti_reg[13].ff_inst
   Register : CNT01.Couti_reg[14].ff_inst
   Register : CNT01.Couti_reg[15].ff_inst
   Register : CNT02.Couti_reg[0].ff_inst
   Register : CNT02.Couti_reg[1].ff_inst
   Register : CNT02.Couti_reg[2].ff_inst
   Register : CNT02.Couti_reg[3].ff_inst
   Register : CNT02.Couti_reg[4].ff_inst
   Register : CNT02.Couti_reg[5].ff_inst
   Register : CNT02.Couti_reg[6].ff_inst
   Register : CNT02.Couti_reg[7].ff_inst
   Register : CNT02.Couti_reg[8].ff_inst
   Register : CNT02.Couti_reg[9].ff_inst
   Register : CNT02.Couti_reg[10].ff_inst
   Register : CNT02.Couti_reg[11].ff_inst
   Register : CNT02.Couti_reg[12].ff_inst
   Register : CNT02.Couti_reg[13].ff_inst
   Register : CNT02.Couti_reg[14].ff_inst
   Register : CNT02.Couti_reg[15].ff_inst
   Register : CNT03.Couti_reg[0].ff_inst
   Register : CNT03.Couti_reg[1].ff_inst
   Register : CNT03.Couti_reg[2].ff_inst
   Register : CNT03.Couti_reg[3].ff_inst
   Register : CNT03.Couti_reg[4].ff_inst
   Register : CNT03.Couti_reg[5].ff_inst
   Register : CNT03.Couti_reg[6].ff_inst
   Register : CNT03.Couti_reg[7].ff_inst
   Register : CNT03.Couti_reg[8].ff_inst
   Register : CNT03.Couti_reg[9].ff_inst
   Register : CNT03.Couti_reg[10].ff_inst
   Register : CNT03.Couti_reg[11].ff_inst
   Register : CNT03.Couti_reg[12].ff_inst
   Register : CNT03.Couti_reg[13].ff_inst
   Register : CNT03.Couti_reg[14].ff_inst
   Register : CNT03.Couti_reg[15].ff_inst
   Register : CNT04.Couti_reg[0].ff_inst
   Register : CNT04.Couti_reg[1].ff_inst
   Register : CNT04.Couti_reg[2].ff_inst
   Register : CNT04.Couti_reg[3].ff_inst
   Register : CNT04.Couti_reg[4].ff_inst
   Register : CNT04.Couti_reg[5].ff_inst
   Register : CNT04.Couti_reg[6].ff_inst
   Register : CNT04.Couti_reg[7].ff_inst
   Register : CNT04.Couti_reg[8].ff_inst
   Register : CNT04.Couti_reg[9].ff_inst

   Register : CNT04.Couti_reg[10].ff_inst
   Register : CNT04.Couti_reg[11].ff_inst
   Register : CNT04.Couti_reg[12].ff_inst
   Register : CNT04.Couti_reg[13].ff_inst
   Register : CNT04.Couti_reg[14].ff_inst
   Register : CNT04.Couti_reg[15].ff_inst
   Register : LED4_0io.PIC_inst
   Register : LED3_0io.PIC_inst
   Register : LED2_0io.PIC_inst
   Register : LED1_0io.PIC_inst

Components with synchronous local reset also reset by asynchronous GSR
----------------------------------------------------------------------

These components have the GSR property set to ENABLED and the local reset is
     synchronous. The components will respond to the synchronous local reset and
     to the unrelated asynchronous reset signal
     'top_reveal_coretop_instance.core0.reset_rvl_n' via the GSR component.

Type and number of components of the type:
   Register = 545
   EBR_CORE = 2

Type and instance name of component:
   Register : secured_comp_221
   Register : secured_comp_222
   Register : secured_comp_223
   Register : secured_comp_224
   Register : secured_comp_225
   Register : secured_comp_226
   Register : secured_comp_227
   Register : secured_comp_228
   Register : secured_comp_229
   Register : secured_comp_230
   Register : secured_comp_231
   Register : secured_comp_232
   Register : secured_comp_233
   Register : secured_comp_234
   Register : secured_comp_235
   Register : secured_comp_236
   Register : secured_comp_237
   Register : secured_comp_238
   Register : secured_comp_239
   Register : secured_comp_240
   Register : secured_comp_241
   Register : secured_comp_242
   Register : secured_comp_243
   Register : secured_comp_244
   Register : secured_comp_245
   Register : secured_comp_246
   Register : secured_comp_247
   Register : secured_comp_248
   Register : secured_comp_249
   Register : secured_comp_250
   Register : secured_comp_251
   Register : secured_comp_252
   Register : secured_comp_253
   Register : secured_comp_254
   Register : secured_comp_255
   Register : secured_comp_256
   Register : secured_comp_257

   Register : secured_comp_258
   Register : secured_comp_259
   Register : secured_comp_260
   Register : secured_comp_261
   Register : secured_comp_262
   Register : secured_comp_263
   Register : secured_comp_264
   Register : secured_comp_265
   Register : secured_comp_266
   Register : secured_comp_267
   Register : secured_comp_268
   Register : secured_comp_269
   Register : secured_comp_270
   Register : secured_comp_271
   Register : secured_comp_272
   Register : secured_comp_273
   Register : secured_comp_274
   Register : secured_comp_275
   Register : secured_comp_276
   Register : secured_comp_277
   Register : secured_comp_278
   Register : secured_comp_279
   Register : secured_comp_280
   Register : secured_comp_281
   Register : secured_comp_282
   Register : secured_comp_283
   Register : secured_comp_284
   Register : secured_comp_285
   Register : secured_comp_288
   Register : secured_comp_289
   Register : secured_comp_290
   Register : secured_comp_291
   Register : secured_comp_292
   Register : secured_comp_293
   Register : secured_comp_294
   Register : secured_comp_295
   Register : secured_comp_296
   Register : secured_comp_297
   Register : secured_comp_363
   Register : secured_comp_364
   Register : secured_comp_365
   Register : secured_comp_366
   Register : secured_comp_367
   Register : secured_comp_368
   Register : secured_comp_369
   Register : secured_comp_370
   Register : secured_comp_371
   Register : secured_comp_372
   Register : secured_comp_373
   Register : secured_comp_374
   Register : secured_comp_375
   Register : secured_comp_376
   Register : secured_comp_377
   Register : secured_comp_378
   Register : secured_comp_379
   Register : secured_comp_380
   Register : secured_comp_381

   Register : secured_comp_382
   Register : secured_comp_383
   Register : secured_comp_384
   Register : secured_comp_385
   Register : secured_comp_386
   Register : secured_comp_387
   Register : secured_comp_388
   Register : secured_comp_389
   Register : secured_comp_390
   Register : secured_comp_391
   Register : secured_comp_392
   Register : secured_comp_393
   Register : secured_comp_394
   Register : secured_comp_395
   Register : secured_comp_396
   Register : secured_comp_397
   Register : secured_comp_398
   Register : secured_comp_399
   Register : secured_comp_400
   Register : secured_comp_401
   Register : secured_comp_402
   Register : secured_comp_403
   Register : secured_comp_404
   Register : secured_comp_405
   Register : secured_comp_406
   Register : secured_comp_407
   Register : secured_comp_408
   Register : secured_comp_409
   Register : secured_comp_410
   Register : secured_comp_411
   Register : secured_comp_412
   Register : secured_comp_413
   Register : secured_comp_414
   Register : secured_comp_415
   Register : secured_comp_416
   Register : secured_comp_417
   Register : secured_comp_418
   Register : secured_comp_419
   Register : secured_comp_420
   Register : secured_comp_421
   Register : secured_comp_422
   Register : secured_comp_423
   Register : secured_comp_424
   Register : secured_comp_425
   Register : secured_comp_426
   Register : secured_comp_427
   Register : secured_comp_428
   Register : secured_comp_429
   Register : secured_comp_430
   Register : secured_comp_431
   Register : secured_comp_432
   Register : secured_comp_441
   Register : secured_comp_442
   Register : secured_comp_443
   Register : secured_comp_444
   Register : secured_comp_445
   Register : secured_comp_446

   Register : secured_comp_447
   Register : secured_comp_448
   Register : secured_comp_449
   Register : secured_comp_450
   Register : secured_comp_451
   Register : secured_comp_452
   Register : secured_comp_453
   Register : secured_comp_454
   Register : secured_comp_455
   Register : secured_comp_456
   Register : secured_comp_457
   Register : secured_comp_458
   Register : secured_comp_459
   Register : secured_comp_460
   Register : secured_comp_461
   Register : secured_comp_462
   Register : secured_comp_463
   Register : secured_comp_464
   Register : secured_comp_465
   Register : secured_comp_466
   Register : secured_comp_467
   Register : secured_comp_468
   Register : secured_comp_469
   Register : secured_comp_470
   Register : secured_comp_471
   Register : secured_comp_472
   Register : secured_comp_473
   Register : secured_comp_474
   Register : secured_comp_475
   Register : secured_comp_476
   Register : secured_comp_477
   Register : secured_comp_478
   Register : secured_comp_479
   Register : secured_comp_480
   Register : secured_comp_481
   Register : secured_comp_482
   Register : secured_comp_483
   Register : secured_comp_484
   Register : secured_comp_485
   Register : secured_comp_486
   Register : secured_comp_487
   Register : secured_comp_952
   Register : secured_comp_953
   Register : secured_comp_954
   Register : secured_comp_955
   Register : secured_comp_968
   Register : secured_comp_969
   Register : secured_comp_970
   Register : secured_comp_971
   Register : secured_comp_1036
   Register : secured_comp_1037
   Register : secured_comp_1038
   Register : secured_comp_1039
   Register : secured_comp_1040
   Register : secured_comp_1041
   Register : secured_comp_1042
   Register : secured_comp_1043

   Register : secured_comp_1044
   Register : secured_comp_1045
   Register : secured_comp_1046
   Register : secured_comp_1047
   Register : secured_comp_1048
   Register : secured_comp_1049
   Register : secured_comp_1126
   Register : secured_comp_1127
   Register : secured_comp_1144
   Register : secured_comp_1145
   Register : secured_comp_1146
   Register : secured_comp_1147
   Register : secured_comp_1148
   Register : secured_comp_1149
   Register : secured_comp_1150
   Register : secured_comp_1151
   Register : secured_comp_1152
   Register : secured_comp_1153
   Register : secured_comp_1155
   Register : secured_comp_1156
   Register : secured_comp_1157
   Register : secured_comp_1158
   Register : secured_comp_1159
   Register : secured_comp_1236
   Register : secured_comp_1237
   Register : secured_comp_1254
   Register : secured_comp_1255
   Register : secured_comp_1256
   Register : secured_comp_1257
   Register : secured_comp_1258
   Register : secured_comp_1259
   Register : secured_comp_1260
   Register : secured_comp_1261
   Register : secured_comp_1262
   Register : secured_comp_1263
   Register : secured_comp_1265
   Register : secured_comp_1266
   Register : secured_comp_1267
   Register : secured_comp_1268
   Register : secured_comp_1269
   Register : secured_comp_1350
   Register : secured_comp_1351
   Register : secured_comp_1384
   Register : secured_comp_1385
   Register : secured_comp_1386
   Register : secured_comp_1387
   Register : secured_comp_1388
   Register : secured_comp_1389
   Register : secured_comp_1390
   Register : secured_comp_1391
   Register : secured_comp_1392
   Register : secured_comp_1393
   Register : secured_comp_1395
   Register : secured_comp_1396
   Register : secured_comp_1397
   Register : secured_comp_1398
   Register : secured_comp_1399

   Register : secured_comp_1494
   Register : secured_comp_1495
   Register : secured_comp_1496
   Register : secured_comp_1497
   Register : secured_comp_1498
   Register : secured_comp_1499
   Register : secured_comp_1500
   Register : secured_comp_1501
   Register : secured_comp_1502
   Register : secured_comp_1503
   Register : secured_comp_1504
   Register : secured_comp_1505
   Register : secured_comp_1506
   Register : secured_comp_1507
   Register : secured_comp_1508
   Register : secured_comp_1509
   Register : secured_comp_1510
   Register : secured_comp_1511
   Register : secured_comp_1512
   Register : secured_comp_1513
   Register : secured_comp_1514
   Register : secured_comp_1515
   Register : secured_comp_1516
   Register : secured_comp_1517
   Register : secured_comp_1518
   Register : secured_comp_1519
   Register : secured_comp_1520
   Register : secured_comp_1521
   Register : secured_comp_1522
   Register : secured_comp_1523
   Register : secured_comp_1524
   Register : secured_comp_1525
   Register : secured_comp_1526
   Register : secured_comp_1527
   Register : secured_comp_1528
   Register : secured_comp_1529
   Register : secured_comp_1530
   Register : secured_comp_1531
   Register : secured_comp_1532
   Register : secured_comp_1533
   Register : secured_comp_1534
   Register : secured_comp_1535
   Register : secured_comp_1536
   Register : secured_comp_1537
   Register : secured_comp_1538
   Register : secured_comp_1539
   Register : secured_comp_1540
   Register : secured_comp_1541
   Register : secured_comp_1542
   Register : secured_comp_1543
   Register : secured_comp_1544
   Register : secured_comp_1545
   Register : secured_comp_1546
   Register : secured_comp_1547
   Register : secured_comp_1548
   Register : secured_comp_1549
   Register : secured_comp_1550

   Register : secured_comp_1551
   Register : secured_comp_1552
   Register : secured_comp_1553
   Register : secured_comp_1554
   Register : secured_comp_1555
   Register : secured_comp_1556
   Register : secured_comp_1557
   Register : secured_comp_1558
   Register : secured_comp_1559
   Register : secured_comp_1560
   Register : secured_comp_1561
   Register : secured_comp_1656
   Register : secured_comp_1657
   Register : secured_comp_1658
   Register : secured_comp_1659
   Register : secured_comp_1660
   Register : secured_comp_1661
   Register : secured_comp_1662
   Register : secured_comp_1663
   Register : secured_comp_1664
   Register : secured_comp_1665
   Register : secured_comp_1666
   Register : secured_comp_1667
   Register : secured_comp_1668
   Register : secured_comp_1669
   Register : secured_comp_1670
   Register : secured_comp_1671
   Register : secured_comp_1672
   Register : secured_comp_1673
   Register : secured_comp_1674
   Register : secured_comp_1675
   Register : secured_comp_1676
   Register : secured_comp_1677
   Register : secured_comp_1678
   Register : secured_comp_1679
   Register : secured_comp_1680
   Register : secured_comp_1681
   Register : secured_comp_1682
   Register : secured_comp_1683
   Register : secured_comp_1684
   Register : secured_comp_1685
   Register : secured_comp_1686
   Register : secured_comp_1687
   Register : secured_comp_1688
   Register : secured_comp_1689
   Register : secured_comp_1690
   Register : secured_comp_1691
   Register : secured_comp_1692
   Register : secured_comp_1693
   Register : secured_comp_1694
   Register : secured_comp_1695
   Register : secured_comp_1696
   Register : secured_comp_1697
   Register : secured_comp_1698
   Register : secured_comp_1699
   Register : secured_comp_1700
   Register : secured_comp_1701

   Register : secured_comp_1702
   Register : secured_comp_1703
   Register : secured_comp_1704
   Register : secured_comp_1705
   Register : secured_comp_1706
   Register : secured_comp_1707
   Register : secured_comp_1708
   Register : secured_comp_1709
   Register : secured_comp_1710
   Register : secured_comp_1711
   Register : secured_comp_1712
   Register : secured_comp_1713
   Register : secured_comp_1714
   Register : secured_comp_1715
   Register : secured_comp_1716
   Register : secured_comp_1717
   Register : secured_comp_1718
   Register : secured_comp_1719
   Register : secured_comp_1720
   Register : secured_comp_1721
   Register : secured_comp_1722
   Register : secured_comp_1723
   Register : secured_comp_1818
   Register : secured_comp_1819
   Register : secured_comp_1820
   Register : secured_comp_1821
   Register : secured_comp_1822
   Register : secured_comp_1823
   Register : secured_comp_1824
   Register : secured_comp_1825
   Register : secured_comp_1826
   Register : secured_comp_1827
   Register : secured_comp_1828
   Register : secured_comp_1829
   Register : secured_comp_1830
   Register : secured_comp_1831
   Register : secured_comp_1832
   Register : secured_comp_1833
   Register : secured_comp_1834
   Register : secured_comp_1835
   Register : secured_comp_1836
   Register : secured_comp_1837
   Register : secured_comp_1838
   Register : secured_comp_1839
   Register : secured_comp_1840
   Register : secured_comp_1841
   Register : secured_comp_1842
   Register : secured_comp_1843
   Register : secured_comp_1844
   Register : secured_comp_1845
   Register : secured_comp_1846
   Register : secured_comp_1847
   Register : secured_comp_1848
   Register : secured_comp_1849
   Register : secured_comp_1850
   Register : secured_comp_1851
   Register : secured_comp_1852

   Register : secured_comp_1853
   Register : secured_comp_1854
   Register : secured_comp_1855
   Register : secured_comp_1856
   Register : secured_comp_1857
   Register : secured_comp_1858
   Register : secured_comp_1859
   Register : secured_comp_1860
   Register : secured_comp_1861
   Register : secured_comp_1862
   Register : secured_comp_1863
   Register : secured_comp_1864
   Register : secured_comp_1865
   Register : secured_comp_1866
   Register : secured_comp_1867
   Register : secured_comp_1868
   Register : secured_comp_1869
   Register : secured_comp_1870
   Register : secured_comp_1871
   Register : secured_comp_1872
   Register : secured_comp_1873
   Register : secured_comp_1874
   Register : secured_comp_1875
   Register : secured_comp_1876
   Register : secured_comp_1877
   Register : secured_comp_1878
   Register : secured_comp_1879
   Register : secured_comp_1880
   Register : secured_comp_1881
   Register : secured_comp_1882
   Register : secured_comp_1883
   Register : secured_comp_1884
   Register : secured_comp_1885
   Register : secured_comp_1980
   Register : secured_comp_1981
   Register : secured_comp_1982
   Register : secured_comp_1983
   Register : secured_comp_1984
   Register : secured_comp_1985
   Register : secured_comp_1986
   Register : secured_comp_1987
   Register : secured_comp_1988
   Register : secured_comp_1989
   Register : secured_comp_1990
   Register : secured_comp_1991
   Register : secured_comp_1992
   Register : secured_comp_1993
   Register : secured_comp_1994
   Register : secured_comp_1995
   Register : secured_comp_1996
   Register : secured_comp_1997
   Register : secured_comp_1998
   Register : secured_comp_1999
   Register : secured_comp_2000
   Register : secured_comp_2001
   Register : secured_comp_2002
   Register : secured_comp_2003

   Register : secured_comp_2004
   Register : secured_comp_2005
   Register : secured_comp_2006
   Register : secured_comp_2007
   Register : secured_comp_2008
   Register : secured_comp_2009
   Register : secured_comp_2010
   Register : secured_comp_2011
   Register : secured_comp_2012
   Register : secured_comp_2013
   Register : secured_comp_2014
   Register : secured_comp_2015
   Register : secured_comp_2016
   Register : secured_comp_2017
   Register : secured_comp_2018
   Register : secured_comp_2019
   Register : secured_comp_2020
   Register : secured_comp_2021
   Register : secured_comp_2022
   Register : secured_comp_2023
   Register : secured_comp_2024
   Register : secured_comp_2025
   Register : secured_comp_2026
   Register : secured_comp_2027
   Register : secured_comp_2028
   Register : secured_comp_2029
   Register : secured_comp_2030
   Register : secured_comp_2031
   Register : secured_comp_2032
   Register : secured_comp_2033
   Register : secured_comp_2034
   Register : secured_comp_2035
   Register : secured_comp_2036
   Register : secured_comp_2037
   Register : secured_comp_2038
   Register : secured_comp_2039
   Register : secured_comp_2040
   Register : secured_comp_2041
   Register : secured_comp_2042
   Register : secured_comp_2043
   Register : secured_comp_2044
   Register : secured_comp_2045
   Register : secured_comp_2046
   Register : secured_comp_2047
   Register : secured_comp_2065
   Register : secured_comp_2066
   Register : secured_comp_2067
   Register : secured_comp_2068
   Register : secured_comp_2069
   Register : secured_comp_2070
   Register : secured_comp_2071
   Register : secured_comp_2072
   EBR_CORE : secured_comp_286
   EBR_CORE : secured_comp_287

Block RAM components with enabled GSR
-------------------------------

These Block RAM components have the GSR property set to ENABLED. The components

     will respond to the asynchronous reset signal
     'top_reveal_coretop_instance.core0.reset_rvl_n' via the GSR component.

Type and number of components of the type:
   EBR_CORE = 2

Type and instance name of component:
   EBR_CORE : secured_comp_286
   EBR_CORE : secured_comp_287



Constraint Summary
------------------

   Total number of constraints: 17
   Total number of constraints dropped: 0



Run Time and Memory Usage
-------------------------

   Total CPU Time: 14 secs
   Total REAL Time: 15 secs
   Peak Memory Usage: 603 MB








































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