Synthesis Report #Build: Synplify Pro (R) U-2023.03LR-1, Build 098R, May 29 2023 #install: C:\lscc\radiant\2023.1\synpbase #OS: Windows 10 or later #Hostname: DESKTOP-CQ0R02Q # Fri Dec 1 10:23:25 2023 #Implementation: impl1 Copyright (C) 1994-2023 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: U-2023.03LR-1 Install: C:\lscc\radiant\2023.1\synpbase OS: Windows 10 or later Hostname: DESKTOP-CQ0R02Q Implementation : impl1 Synopsys HDL Compiler, Version comp202303synp1, Build 100R, Built May 29 2023 11:23:06, @ @N|Running in 64-bit mode ###########################################################[ Copyright (C) 1994-2023 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: U-2023.03LR-1 Install: C:\lscc\radiant\2023.1\synpbase OS: Windows 10 or later Hostname: DESKTOP-CQ0R02Q Implementation : impl1 Synopsys VHDL Compiler, Version comp202303synp1, Build 100R, Built May 29 2023 11:23:06, @ @N|Running in 64-bit mode @N:"D:\02_LSCC\09_GSR\Final\LAB04_GSR_LSR\source\impl1\Top.vhd":8:7:8:9|Top entity is set to Top. @N: CD140 : | Using the VHDL 1993 Standard for file 'C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.vhd'. @N: CD140 : | Using the VHDL 1993 Standard for file 'D:\02_LSCC\09_GSR\Final\LAB04_GSR_LSR\source\impl1\Reset_Sync.vhd'. @N: CD140 : | Using the VHDL 1993 Standard for file 'D:\02_LSCC\09_GSR\Final\LAB04_GSR_LSR\source\impl1\CNT.vhd'. @N: CD140 : | Using the VHDL 1993 Standard for file 'D:\02_LSCC\09_GSR\Final\LAB04_GSR_LSR\source\impl1\MyPackage.vhd'. @N: CD140 : | Using the VHDL 1993 Standard for file 'C:\lscc\radiant\2023.1\cae_library\synthesis\vhdl\lfcpnx.vhd'. @N: CD140 : | Using the VHDL 1993 Standard for file 'D:\02_LSCC\09_GSR\Final\LAB04_GSR_LSR\source\impl1\Top.vhd'. VHDL syntax check successful! At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 102MB) Process completed successfully. # Fri Dec 1 10:23:26 2023 ###########################################################] ###########################################################[ Copyright (C) 1994-2023 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: U-2023.03LR-1 Install: C:\lscc\radiant\2023.1\synpbase OS: Windows 10 or later Hostname: DESKTOP-CQ0R02Q Implementation : impl1 Synopsys Verilog Compiler, Version comp202303synp1, Build 100R, Built May 29 2023 11:23:06, @ @N|Running in 64-bit mode @I::"C:\lscc\radiant\2023.1\synpbase\lib\lucent\lfcpnx.v" (library work) @I::"C:\lscc\radiant\2023.1\synpbase\lib\lucent\pmi_def.v" (library work) @I::"C:\lscc\radiant\2023.1\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__) @I::"C:\lscc\radiant\2023.1\synpbase\lib\vlog\scemi_objects.v" (library snps_haps) @I::"C:\lscc\radiant\2023.1\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps) @I::"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v" (library work) @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_addsub.v" (library work) @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_addsub.v":"C:\lscc\radiant\2023.1\ip\pmi\../common/adder_subtractor/rtl\lscc_add_sub.v" (library work) @N: CG334 :"C:\lscc\radiant\2023.1\ip\pmi\../common/adder_subtractor/rtl\lscc_add_sub.v":313:13:313:25|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\2023.1\ip\pmi\../common/adder_subtractor/rtl\lscc_add_sub.v":333:13:333:24|Read directive translate_on. @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_add.v" (library work) @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_add.v":"C:\lscc\radiant\2023.1\ip\pmi\../common/adder/rtl\lscc_adder.v" (library work) @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_complex_mult.v" (library work) @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_complex_mult.v":"C:\lscc\radiant\2023.1\ip\pmi\../common/complex_mult/rtl\lscc_complex_mult.v" (library work) @N: CG334 :"C:\lscc\radiant\2023.1\ip\pmi\pmi_complex_mult.v":92:11:92:23|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\2023.1\ip\pmi\pmi_complex_mult.v":101:11:101:22|Read directive translate_on. @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_counter.v" (library work) @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_counter.v":"C:\lscc\radiant\2023.1\ip\pmi\../common/counter/rtl\lscc_cntr.v" (library work) @N: CG334 :"C:\lscc\radiant\2023.1\ip\pmi\../common/counter/rtl\lscc_cntr.v":129:13:129:25|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\2023.1\ip\pmi\../common/counter/rtl\lscc_cntr.v":143:13:143:24|Read directive translate_on. @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_distributed_dpram.v" (library work) @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_distributed_dpram.v":"C:\lscc\radiant\2023.1\ip\pmi\../common/distributed_dpram/rtl\lscc_distributed_dpram.v" (library work) @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_distributed_spram.v" (library work) @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_distributed_spram.v":"C:\lscc\radiant\2023.1\ip\pmi\../common/distributed_spram/rtl\lscc_distributed_spram.v" (library work) @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_distributed_rom.v" (library work) @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_distributed_rom.v":"C:\lscc\radiant\2023.1\ip\pmi\../common/distributed_rom/rtl\lscc_distributed_rom.v" (library work) @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_distributed_shift_reg.v" (library work) @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_distributed_shift_reg.v":"C:\lscc\radiant\2023.1\ip\pmi\../common/ram_shift_reg/rtl\lscc_shift_register.v" (library work) @N: CG334 :"C:\lscc\radiant\2023.1\ip\pmi\pmi_distributed_shift_reg.v":126:11:126:23|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\2023.1\ip\pmi\pmi_distributed_shift_reg.v":135:11:135:22|Read directive translate_on. @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_fifo.v" (library work) @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_fifo.v":"C:\lscc\radiant\2023.1\ip\pmi\../avant/fifo/rtl\lscc_fifo.v" (library work) @N: CG334 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/fifo/rtl\lscc_fifo.v":3267:17:3267:29|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/fifo/rtl\lscc_fifo.v":3274:17:3274:28|Read directive translate_on. @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_fifo_dc.v" (library work) @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_fifo_dc.v":"C:\lscc\radiant\2023.1\ip\pmi\../avant/fifo_dc/rtl\lscc_fifo_dc.v" (library work) @N: CG334 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/fifo_dc/rtl\lscc_fifo_dc.v":4907:25:4907:37|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/fifo_dc/rtl\lscc_fifo_dc.v":4911:25:4911:36|Read directive translate_on. @N: CG334 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/fifo_dc/rtl\lscc_fifo_dc.v":4942:29:4942:41|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/fifo_dc/rtl\lscc_fifo_dc.v":4946:29:4946:40|Read directive translate_on. @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_mac.v" (library work) @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_mac.v":"C:\lscc\radiant\2023.1\ip\pmi\../common/mult_accumulate/rtl\lscc_mult_accumulate.v" (library work) @N: CG334 :"C:\lscc\radiant\2023.1\ip\pmi\pmi_mac.v":94:11:94:23|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\2023.1\ip\pmi\pmi_mac.v":109:11:109:22|Read directive translate_on. @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_multaddsubsum.v" (library work) @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_multaddsubsum.v":"C:\lscc\radiant\2023.1\ip\pmi\../common/mult_add_sub_sum/rtl\lscc_mult_add_sub_sum.v" (library work) @N: CG334 :"C:\lscc\radiant\2023.1\ip\pmi\../common/mult_add_sub_sum/rtl\lscc_mult_add_sub_sum.v":210:13:210:25|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\2023.1\ip\pmi\../common/mult_add_sub_sum/rtl\lscc_mult_add_sub_sum.v":227:13:227:24|Read directive translate_on. @N: CG334 :"C:\lscc\radiant\2023.1\ip\pmi\pmi_multaddsubsum.v":84:11:84:23|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\2023.1\ip\pmi\pmi_multaddsubsum.v":93:11:93:22|Read directive translate_on. @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_multaddsub.v" (library work) @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_multaddsub.v":"C:\lscc\radiant\2023.1\ip\pmi\../common/mult_add_sub/rtl\lscc_mult_add_sub.v" (library work) @N: CG334 :"C:\lscc\radiant\2023.1\ip\pmi\pmi_multaddsub.v":91:11:91:23|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\2023.1\ip\pmi\pmi_multaddsub.v":100:11:100:22|Read directive translate_on. @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_mult.v" (library work) @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_mult.v":"C:\lscc\radiant\2023.1\ip\pmi\../common/multiplier/rtl\lscc_multiplier.v" (library work) @N: CG334 :"C:\lscc\radiant\2023.1\ip\pmi\pmi_mult.v":87:11:87:23|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\2023.1\ip\pmi\pmi_mult.v":96:11:96:22|Read directive translate_on. @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_ram_dp.v" (library work) @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_ram_dp.v":"C:\lscc\radiant\2023.1\ip\pmi\../avant/ram_dp/rtl\lscc_ram_dp.v" (library work) @N: CG334 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/ram_dp/rtl\lscc_ram_dp.v":1059:25:1059:37|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/ram_dp/rtl\lscc_ram_dp.v":1063:25:1063:36|Read directive translate_on. @N: CG334 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/ram_dp/rtl\lscc_ram_dp.v":1094:29:1094:41|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/ram_dp/rtl\lscc_ram_dp.v":1098:29:1098:40|Read directive translate_on. @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_ram_dp_be.v" (library work) @N: CG334 :"C:\lscc\radiant\2023.1\ip\pmi\pmi_ram_dp_be.v":146:11:146:23|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\2023.1\ip\pmi\pmi_ram_dp_be.v":155:11:155:22|Read directive translate_on. @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_ram_dp_true.v" (library work) @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_ram_dp_true.v":"C:\lscc\radiant\2023.1\ip\pmi\../avant/ram_dp_true/rtl\lscc_ram_dp_true.v" (library work) @N: CG334 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/ram_dp_true/rtl\lscc_ram_dp_true.v":1876:29:1876:41|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/ram_dp_true/rtl\lscc_ram_dp_true.v":1881:29:1881:40|Read directive translate_on. @N: CG334 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/ram_dp_true/rtl\lscc_ram_dp_true.v":1912:33:1912:45|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/ram_dp_true/rtl\lscc_ram_dp_true.v":1916:33:1916:44|Read directive translate_on. @N: CG334 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/ram_dp_true/rtl\lscc_ram_dp_true.v":1949:29:1949:41|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/ram_dp_true/rtl\lscc_ram_dp_true.v":1954:29:1954:40|Read directive translate_on. @N: CG334 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/ram_dp_true/rtl\lscc_ram_dp_true.v":1984:33:1984:45|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/ram_dp_true/rtl\lscc_ram_dp_true.v":1988:33:1988:44|Read directive translate_on. @N: CG334 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/ram_dp_true/rtl\lscc_ram_dp_true.v":2504:29:2504:41|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/ram_dp_true/rtl\lscc_ram_dp_true.v":2509:29:2509:40|Read directive translate_on. @N: CG334 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/ram_dp_true/rtl\lscc_ram_dp_true.v":2540:33:2540:45|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/ram_dp_true/rtl\lscc_ram_dp_true.v":2544:33:2544:44|Read directive translate_on. @N: CG334 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/ram_dp_true/rtl\lscc_ram_dp_true.v":2577:29:2577:41|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/ram_dp_true/rtl\lscc_ram_dp_true.v":2582:29:2582:40|Read directive translate_on. @N: CG334 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/ram_dp_true/rtl\lscc_ram_dp_true.v":2613:33:2613:45|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/ram_dp_true/rtl\lscc_ram_dp_true.v":2617:33:2617:44|Read directive translate_on. @N: CG334 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/ram_dp_true/rtl\lscc_ram_dp_true.v":3104:29:3104:41|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/ram_dp_true/rtl\lscc_ram_dp_true.v":3109:29:3109:40|Read directive translate_on. @N: CG334 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/ram_dp_true/rtl\lscc_ram_dp_true.v":3140:33:3140:45|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/ram_dp_true/rtl\lscc_ram_dp_true.v":3144:33:3144:44|Read directive translate_on. @N: CG334 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/ram_dp_true/rtl\lscc_ram_dp_true.v":3177:29:3177:41|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/ram_dp_true/rtl\lscc_ram_dp_true.v":3182:29:3182:40|Read directive translate_on. @N: CG334 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/ram_dp_true/rtl\lscc_ram_dp_true.v":3213:33:3213:45|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/ram_dp_true/rtl\lscc_ram_dp_true.v":3217:33:3217:44|Read directive translate_on. @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_ram_dq.v" (library work) @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_ram_dq.v":"C:\lscc\radiant\2023.1\ip\pmi\../avant/ram_dq/rtl\lscc_ram_dq.v" (library work) @N: CG334 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/ram_dq/rtl\lscc_ram_dq.v":1481:25:1481:37|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/ram_dq/rtl\lscc_ram_dq.v":1487:25:1487:36|Read directive translate_on. @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_ram_dq_be.v" (library work) @N: CG334 :"C:\lscc\radiant\2023.1\ip\pmi\pmi_ram_dq_be.v":87:11:87:23|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\2023.1\ip\pmi\pmi_ram_dq_be.v":95:11:95:22|Read directive translate_on. @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_rom.v" (library work) @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_rom.v":"C:\lscc\radiant\2023.1\ip\pmi\../avant/rom/rtl\lscc_rom.v" (library work) @N: CG334 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/rom/rtl\lscc_rom.v":969:25:969:37|Read directive translate_off. @N: CG333 :"C:\lscc\radiant\2023.1\ip\pmi\../avant/rom/rtl\lscc_rom.v":975:25:975:36|Read directive translate_on. @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.v":"C:\lscc\radiant\2023.1\ip\pmi\pmi_sub.v" (library work) @I:"C:\lscc\radiant\2023.1\ip\pmi\pmi_sub.v":"C:\lscc\radiant\2023.1\ip\pmi\../common/subtractor/rtl\lscc_subtractor.v" (library work) Verilog syntax check successful! At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 130MB peak: 130MB) Process completed successfully. # Fri Dec 1 10:23:26 2023 ###########################################################] ###########################################################[ @N:"D:\02_LSCC\09_GSR\Final\LAB04_GSR_LSR\source\impl1\Top.vhd":8:7:8:9|Top entity is set to Top. File C:\lscc\radiant\2023.1\synpbase\lib\vhd\signed.vhd changed - recompiling @N: CD140 : | Using the VHDL 1993 Standard for file 'C:\lscc\radiant\2023.1\ip\pmi\pmi_lfcpnx.vhd'. @N: CD140 : | Using the VHDL 1993 Standard for file 'D:\02_LSCC\09_GSR\Final\LAB04_GSR_LSR\source\impl1\Reset_Sync.vhd'. @N: CD140 : | Using the VHDL 1993 Standard for file 'D:\02_LSCC\09_GSR\Final\LAB04_GSR_LSR\source\impl1\CNT.vhd'. @N: CD140 : | Using the VHDL 1993 Standard for file 'D:\02_LSCC\09_GSR\Final\LAB04_GSR_LSR\source\impl1\MyPackage.vhd'. @N: CD140 : | Using the VHDL 1993 Standard for file 'C:\lscc\radiant\2023.1\cae_library\synthesis\vhdl\lfcpnx.vhd'. @N: CD140 : | Using the VHDL 1993 Standard for file 'D:\02_LSCC\09_GSR\Final\LAB04_GSR_LSR\source\impl1\Top.vhd'. VHDL syntax check successful! @N: CD630 :"D:\02_LSCC\09_GSR\Final\LAB04_GSR_LSR\source\impl1\Top.vhd":8:7:8:9|Synthesizing work.top.behave. @N: CD630 :"D:\02_LSCC\09_GSR\Final\LAB04_GSR_LSR\source\impl1\CNT.vhd":6:7:6:9|Synthesizing work.cnt.rtl. Post processing for work.cnt.rtl Running optimization stage 1 on CNT ....... Finished optimization stage 1 on CNT (CPU Time 0h:00m:00s, Memory Used current: 104MB peak: 105MB) @N: CD630 :"D:\02_LSCC\09_GSR\Final\LAB04_GSR_LSR\source\impl1\Reset_Sync.vhd":6:7:6:16|Synthesizing work.reset_sync.rtl. Post processing for work.reset_sync.rtl Running optimization stage 1 on Reset_Sync ....... Finished optimization stage 1 on Reset_Sync (CPU Time 0h:00m:00s, Memory Used current: 104MB peak: 105MB) Post processing for work.top.behave Running optimization stage 1 on Top ....... Finished optimization stage 1 on Top (CPU Time 0h:00m:00s, Memory Used current: 104MB peak: 105MB) Running optimization stage 2 on Reset_Sync ....... Finished optimization stage 2 on Reset_Sync (CPU Time 0h:00m:00s, Memory Used current: 104MB peak: 105MB) Running optimization stage 2 on CNT_16 ....... Finished optimization stage 2 on CNT_16 (CPU Time 0h:00m:00s, Memory Used current: 104MB peak: 105MB) Running optimization stage 2 on Top ....... Finished optimization stage 2 on Top (CPU Time 0h:00m:00s, Memory Used current: 104MB peak: 105MB) For a summary of runtime per design unit, please see file: ========================================================== @L: D:\02_LSCC\09_GSR\Final\LAB04_GSR_LSR\impl1\synwork\layer0.duruntime At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 102MB) Process completed successfully. # Fri Dec 1 10:23:26 2023 ###########################################################] ###########################################################[ Copyright (C) 1994-2023 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: U-2023.03LR-1 Install: C:\lscc\radiant\2023.1\synpbase OS: Windows 10 or later Hostname: DESKTOP-CQ0R02Q Implementation : impl1 Synopsys Synopsys Netlist Linker, Version comp202303synp1, Build 100R, Built May 29 2023 11:23:06, @ @N|Running in 64-bit mode At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 90MB peak: 91MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Fri Dec 1 10:23:26 2023 ###########################################################] For a summary of runtime and memory usage for all design units, please see file: ========================================================== @L: D:\02_LSCC\09_GSR\Final\LAB04_GSR_LSR\impl1\synwork\LAB04_impl1_comp.rt.csv @END At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 23MB peak: 23MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Fri Dec 1 10:23:26 2023 ###########################################################] ###########################################################[ Copyright (C) 1994-2023 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: U-2023.03LR-1 Install: C:\lscc\radiant\2023.1\synpbase OS: Windows 10 or later Hostname: DESKTOP-CQ0R02Q Implementation : impl1 Synopsys Synopsys Netlist Linker, Version comp202303synp1, Build 100R, Built May 29 2023 11:23:06, @ @N|Running in 64-bit mode File D:\02_LSCC\09_GSR\Final\LAB04_GSR_LSR\impl1\synwork\LAB04_impl1_comp.srs changed - recompiling At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 91MB peak: 91MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Fri Dec 1 10:23:28 2023 ###########################################################] # Fri Dec 1 10:23:28 2023 Copyright (C) 1994-2023 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: U-2023.03LR-1 Install: C:\lscc\radiant\2023.1\synpbase OS: Windows 10 or later Hostname: DESKTOP-CQ0R02Q Implementation : impl1 Synopsys Lattice Technology Pre-mapping, Version map202303lat, Build 070R, Built Jun 8 2023 11:14:23, @ Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 122MB peak: 122MB) Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 126MB peak: 136MB) Reading constraint file: D:\02_LSCC\09_GSR\Final\LAB04_GSR_LSR\source\impl1\timingsdc.sdc @L: D:\02_LSCC\09_GSR\Final\LAB04_GSR_LSR\impl1\LAB04_impl1_scck.rpt See clock summary report "D:\02_LSCC\09_GSR\Final\LAB04_GSR_LSR\impl1\LAB04_impl1_scck.rpt" @N: MF916 |Option synthesis_strategy=base is enabled. @N: MF248 |Running in 64-bit mode. @N: MF667 |Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 136MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 136MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 143MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 145MB) NConnInternalConnection caching is on Starting HSTDM IP insertion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 193MB peak: 194MB) Finished HSTDM IP insertion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 193MB peak: 194MB) Started DisTri Cleanup (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 193MB peak: 194MB) Finished DisTri Cleanup (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 193MB peak: 194MB) Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 195MB peak: 195MB) Finished clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 195MB peak: 195MB) @N: FX1184 |Applying syn_allowed_resources blockrams=208 on top level netlist Top Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 195MB peak: 196MB) Clock Summary ****************** Start Requested Requested Clock Clock Clock Level Clock Frequency Period Type Group Load --------------------------------------------------------------------------------------- 0 - CLK1 150.0 MHz 6.667 declared default_clkgroup 19 0 - clk2 150.0 MHz 6.667 declared default_clkgroup 19 ======================================================================================= Clock Load Summary *********************** Clock Source Clock Pin Non-clock Pin Non-clock Pin Clock Load Pin Seq Example Seq Example Comb Example ---------------------------------------------------------------------------------- CLK1 19 CLK1(port) LED1.C - - clk2 19 clk2(port) LED2.C - - ================================================================================== ICG Latch Removal Summary: Number of ICG latches removed: 0 Number of ICG latches not removed: 0 @S |Clock Optimization Summary #### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[ 2 non-gated/non-generated clock tree(s) driving 38 clock pin(s) of sequential element(s) 0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s) 0 instances converted, 0 sequential instances remain driven by gated/generated clocks =========================== Non-Gated/Non-Generated Clocks ============================ Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance --------------------------------------------------------------------------------------- @KP:ckid0_0 clk2 port 19 LED2 @KP:ckid0_1 CLK1 port 19 LED1 ======================================================================================= ##### END OF CLOCK OPTIMIZATION REPORT ###### Summary of user generated gated clocks: 0 user generated gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s) @N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. Finished Pre Mapping Phase. Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 196MB peak: 196MB) Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 196MB peak: 196MB) Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 197MB peak: 197MB) Pre-mapping successful! At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 198MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Fri Dec 1 10:23:29 2023 ###########################################################] Map & Optimize Report # Fri Dec 1 10:23:29 2023 Copyright (C) 1994-2023 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: U-2023.03LR-1 Install: C:\lscc\radiant\2023.1\synpbase OS: Windows 10 or later Hostname: DESKTOP-CQ0R02Q Implementation : impl1 Synopsys Lattice Technology Mapper, Version map202303lat, Build 070R, Built Jun 8 2023 11:14:23, @ Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 122MB peak: 122MB) @N: MF916 |Option synthesis_strategy=base is enabled. @N: MF248 |Running in 64-bit mode. @N: MF667 |Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 124MB peak: 136MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 124MB peak: 136MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 138MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB) Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 192MB peak: 192MB) Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 195MB peak: 195MB) Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 196MB peak: 196MB) Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 196MB peak: 197MB) Available hyper_sources - for debug and ip models None Found NConnInternalConnection caching is on Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 197MB peak: 197MB) Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 197MB peak: 197MB) Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 197MB peak: 198MB) Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 197MB peak: 198MB) Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 197MB peak: 198MB) Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 198MB peak: 198MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:00s 4.52ns 7 / 38 Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 198MB peak: 199MB) @N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 199MB peak: 199MB) Starting CDBProcessSetClockGroups... (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 199MB peak: 199MB) Finished with CDBProcessSetClockGroups (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 199MB peak: 199MB) Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 199MB) Writing Analyst data base D:\02_LSCC\09_GSR\Final\LAB04_GSR_LSR\impl1\synwork\LAB04_impl1_m.srm Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 199MB peak: 199MB) Writing Verilog Simulation files Writing scf file... (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 200MB peak: 200MB) @N: BW103 |The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns. @N: BW107 |Synopsys Constraint File capacitance units using default value of 1pF Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 201MB peak: 201MB) Finished Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 201MB peak: 201MB) Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 200MB peak: 201MB) @N: MT615 |Found clock CLK1 with period 6.67ns @N: MT615 |Found clock clk2 with period 6.67ns ##### START OF TIMING REPORT #####[ # Timing report written on Fri Dec 1 10:23:32 2023 # Top view: Top Requested Frequency: 150.0 MHz Wire load mode: top Paths requested: 5 Constraint File(s): D:\02_LSCC\09_GSR\Final\LAB04_GSR_LSR\source\impl1\timingsdc.sdc @N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. @N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock. Performance Summary ******************* Worst slack in design: 4.169 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ------------------------------------------------------------------------------------------------------------------ CLK1 150.0 MHz 400.4 MHz 6.667 2.498 4.169 declared default_clkgroup clk2 150.0 MHz 400.4 MHz 6.667 2.498 4.169 declared default_clkgroup System 1.0 MHz NA 1000.000 NA NA system system_clkgroup ================================================================================================================== Estimated period and frequency reported as NA means no slack depends directly on the clock waveform Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise -------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack -------------------------------------------------------------------------------------------------------- CLK1 CLK1 | 6.667 4.169 | No paths - | No paths - | No paths - clk2 clk2 | 6.667 4.169 | No paths - | No paths - | No paths - ======================================================================================================== Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: CLK1 ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------- CNT01.Couti[0] CLK1 FD1P3IX Q CNT1[0] 0.838 4.169 CNT01.Couti[1] CLK1 FD1P3IX Q Couti[1] 0.753 4.313 CNT01.Couti[2] CLK1 FD1P3IX Q Couti[2] 0.753 4.313 CNT01.Couti[3] CLK1 FD1P3IX Q Couti[3] 0.753 4.372 CNT01.Couti[4] CLK1 FD1P3IX Q Couti[4] 0.753 4.372 CNT01.Couti[5] CLK1 FD1P3IX Q Couti[5] 0.753 4.431 CNT01.Couti[6] CLK1 FD1P3IX Q Couti[6] 0.753 4.431 CNT01.Couti[7] CLK1 FD1P3IX Q Couti[7] 0.753 4.490 CNT01.Couti[8] CLK1 FD1P3IX Q Couti[8] 0.753 4.490 CNT01.Couti[9] CLK1 FD1P3IX Q Couti[9] 0.753 4.549 =================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------ CNT01.Couti[15] CLK1 FD1P3IX D un3_couti[15] 6.811 4.169 CNT01.Couti[13] CLK1 FD1P3IX D un3_couti[13] 6.811 4.228 CNT01.Couti[14] CLK1 FD1P3IX D un3_couti[14] 6.811 4.228 CNT01.Couti[11] CLK1 FD1P3IX D un3_couti[11] 6.811 4.287 CNT01.Couti[12] CLK1 FD1P3IX D un3_couti[12] 6.811 4.287 CNT01.Couti[9] CLK1 FD1P3IX D un3_couti[9] 6.811 4.346 CNT01.Couti[10] CLK1 FD1P3IX D un3_couti[10] 6.811 4.346 CNT01.Couti[7] CLK1 FD1P3IX D un3_couti[7] 6.811 4.405 CNT01.Couti[8] CLK1 FD1P3IX D un3_couti[8] 6.811 4.405 CNT01.Couti[5] CLK1 FD1P3IX D un3_couti[5] 6.811 4.464 ========================================================================================== Worst Path Information *********************** Path information for path number 1: Requested Period: 6.667 - Setup time: -0.144 + Clock delay at ending point: 0.000 (ideal) = Required time: 6.811 - Propagation time: 2.642 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : 4.169 Number of logic level(s): 9 Starting point: CNT01.Couti[0] / Q Ending point: CNT01.Couti[15] / D The start point is clocked by CLK1 [rising] (rise=0.000 fall=3.333 period=6.667) on pin CK The end point is clocked by CLK1 [rising] (rise=0.000 fall=3.333 period=6.667) on pin CK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------ CNT01.Couti[0] FD1P3IX Q Out 0.838 0.838 r - CNT1[0] Net - - - - 3 CNT01.un3_couti_cry_0_0 CCU2 A1 In 0.000 0.838 r - CNT01.un3_couti_cry_0_0 CCU2 COUT Out 0.784 1.622 r - un3_couti_cry_0 Net - - - - 1 CNT01.un3_couti_cry_1_0 CCU2 CIN In 0.000 1.622 r - CNT01.un3_couti_cry_1_0 CCU2 COUT Out 0.059 1.681 r - un3_couti_cry_2 Net - - - - 1 CNT01.un3_couti_cry_3_0 CCU2 CIN In 0.000 1.681 r - CNT01.un3_couti_cry_3_0 CCU2 COUT Out 0.059 1.740 r - un3_couti_cry_4 Net - - - - 1 CNT01.un3_couti_cry_5_0 CCU2 CIN In 0.000 1.740 r - CNT01.un3_couti_cry_5_0 CCU2 COUT Out 0.059 1.799 r - un3_couti_cry_6 Net - - - - 1 CNT01.un3_couti_cry_7_0 CCU2 CIN In 0.000 1.799 r - CNT01.un3_couti_cry_7_0 CCU2 COUT Out 0.059 1.858 r - un3_couti_cry_8 Net - - - - 1 CNT01.un3_couti_cry_9_0 CCU2 CIN In 0.000 1.858 r - CNT01.un3_couti_cry_9_0 CCU2 COUT Out 0.059 1.917 r - un3_couti_cry_10 Net - - - - 1 CNT01.un3_couti_cry_11_0 CCU2 CIN In 0.000 1.917 r - CNT01.un3_couti_cry_11_0 CCU2 COUT Out 0.059 1.976 r - un3_couti_cry_12 Net - - - - 1 CNT01.un3_couti_cry_13_0 CCU2 CIN In 0.000 1.976 r - CNT01.un3_couti_cry_13_0 CCU2 COUT Out 0.059 2.035 r - un3_couti_cry_14 Net - - - - 1 CNT01.un3_couti_s_15_0 CCU2 CIN In 0.000 2.035 r - CNT01.un3_couti_s_15_0 CCU2 S0 Out 0.607 2.642 r - un3_couti[15] Net - - - - 1 CNT01.Couti[15] FD1P3IX D In 0.000 2.642 r - ========================================================================================== ==================================== Detailed Report for Clock: clk2 ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------- CNT02.Couti[0] clk2 FD1P3IX Q CNT2[0] 0.838 4.169 CNT02.Couti[1] clk2 FD1P3IX Q Couti[1] 0.753 4.313 CNT02.Couti[2] clk2 FD1P3IX Q Couti[2] 0.753 4.313 CNT02.Couti[3] clk2 FD1P3IX Q Couti[3] 0.753 4.372 CNT02.Couti[4] clk2 FD1P3IX Q Couti[4] 0.753 4.372 CNT02.Couti[5] clk2 FD1P3IX Q Couti[5] 0.753 4.431 CNT02.Couti[6] clk2 FD1P3IX Q Couti[6] 0.753 4.431 CNT02.Couti[7] clk2 FD1P3IX Q Couti[7] 0.753 4.490 CNT02.Couti[8] clk2 FD1P3IX Q Couti[8] 0.753 4.490 CNT02.Couti[9] clk2 FD1P3IX Q Couti[9] 0.753 4.549 =================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------ CNT02.Couti[15] clk2 FD1P3IX D un3_couti[15] 6.811 4.169 CNT02.Couti[13] clk2 FD1P3IX D un3_couti[13] 6.811 4.228 CNT02.Couti[14] clk2 FD1P3IX D un3_couti[14] 6.811 4.228 CNT02.Couti[11] clk2 FD1P3IX D un3_couti[11] 6.811 4.287 CNT02.Couti[12] clk2 FD1P3IX D un3_couti[12] 6.811 4.287 CNT02.Couti[9] clk2 FD1P3IX D un3_couti[9] 6.811 4.346 CNT02.Couti[10] clk2 FD1P3IX D un3_couti[10] 6.811 4.346 CNT02.Couti[7] clk2 FD1P3IX D un3_couti[7] 6.811 4.405 CNT02.Couti[8] clk2 FD1P3IX D un3_couti[8] 6.811 4.405 CNT02.Couti[5] clk2 FD1P3IX D un3_couti[5] 6.811 4.464 ========================================================================================== Worst Path Information *********************** Path information for path number 1: Requested Period: 6.667 - Setup time: -0.144 + Clock delay at ending point: 0.000 (ideal) = Required time: 6.811 - Propagation time: 2.642 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : 4.169 Number of logic level(s): 9 Starting point: CNT02.Couti[0] / Q Ending point: CNT02.Couti[15] / D The start point is clocked by clk2 [rising] (rise=0.000 fall=3.333 period=6.667) on pin CK The end point is clocked by clk2 [rising] (rise=0.000 fall=3.333 period=6.667) on pin CK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------ CNT02.Couti[0] FD1P3IX Q Out 0.838 0.838 r - CNT2[0] Net - - - - 3 CNT02.un3_couti_cry_0_0 CCU2 A1 In 0.000 0.838 r - CNT02.un3_couti_cry_0_0 CCU2 COUT Out 0.784 1.622 r - un3_couti_cry_0 Net - - - - 1 CNT02.un3_couti_cry_1_0 CCU2 CIN In 0.000 1.622 r - CNT02.un3_couti_cry_1_0 CCU2 COUT Out 0.059 1.681 r - un3_couti_cry_2 Net - - - - 1 CNT02.un3_couti_cry_3_0 CCU2 CIN In 0.000 1.681 r - CNT02.un3_couti_cry_3_0 CCU2 COUT Out 0.059 1.740 r - un3_couti_cry_4 Net - - - - 1 CNT02.un3_couti_cry_5_0 CCU2 CIN In 0.000 1.740 r - CNT02.un3_couti_cry_5_0 CCU2 COUT Out 0.059 1.799 r - un3_couti_cry_6 Net - - - - 1 CNT02.un3_couti_cry_7_0 CCU2 CIN In 0.000 1.799 r - CNT02.un3_couti_cry_7_0 CCU2 COUT Out 0.059 1.858 r - un3_couti_cry_8 Net - - - - 1 CNT02.un3_couti_cry_9_0 CCU2 CIN In 0.000 1.858 r - CNT02.un3_couti_cry_9_0 CCU2 COUT Out 0.059 1.917 r - un3_couti_cry_10 Net - - - - 1 CNT02.un3_couti_cry_11_0 CCU2 CIN In 0.000 1.917 r - CNT02.un3_couti_cry_11_0 CCU2 COUT Out 0.059 1.976 r - un3_couti_cry_12 Net - - - - 1 CNT02.un3_couti_cry_13_0 CCU2 CIN In 0.000 1.976 r - CNT02.un3_couti_cry_13_0 CCU2 COUT Out 0.059 2.035 r - un3_couti_cry_14 Net - - - - 1 CNT02.un3_couti_s_15_0 CCU2 CIN In 0.000 2.035 r - CNT02.un3_couti_s_15_0 CCU2 S0 Out 0.607 2.642 r - un3_couti[15] Net - - - - 1 CNT02.Couti[15] FD1P3IX D In 0.000 2.642 r - ========================================================================================== ##### END OF TIMING REPORT #####] Timing exceptions that could not be applied Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 201MB peak: 201MB) Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 201MB peak: 201MB) --------------------------------------- Resource Usage Report Part: lfcpnx_100-9 Register bits: 38 of 79872 (0%) PIC Latch: 0 I/O cells: 6 Details: CCU2: 18 FD1P3DX: 4 FD1P3IX: 32 GSR: 1 IB: 4 INV: 5 LUT4: 2 OB: 2 OFD1P3IX: 2 VHI: 5 VLO: 5 Resource Usage inside macros: Registers: 0 LUTs: 0 EBRs: 0 LRAMs: 0 DSPs: 0 Distributed RAMs: 0 Carry Chains: 0 Blackboxes: 0 Mapping Summary: Total number of registers: 38 + 0 = 38 of 79872 (0.05%) Total number of LUTs: 2 + 0 = 2 Total number of EBRs: 0 + 0 = 0 of 208 (0.00%) Total number of LRAMs: 0 + 0 = 0 of 7 (0.00%) Total number of DSPs: 0 + 0 = 0 of 156 (0.00%) Total number of Distributed RAMs: 0 + 0 = 0 Total number of Carry Chains: 18 + 0 = 18 Total number of BlackBoxes: 11 + 0 = 11 Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 62MB peak: 201MB) Process took 0h:00m:02s realtime, 0h:00m:01s cputime # Fri Dec 1 10:23:32 2023 ###########################################################]