Project Settings
Project Name proj_1 Device Name Async_rst: Lattice LFCPNX : LFCPNX_100
Implementation Name Async_rst Top Module Top
Pipelining 1 Retiming 0
Resource Sharing 1 Fanout Guide 1000
Disable I/O Insertion 0 Disable Sequential Optimizations 0
Clock Conversion 0 FSM Compiler 1

Run Status
Job Name Status CPU Time Real Time Memory Date/Time
(compiler)Complete 156 30 0 - 00m:26s - 10/9/2023
9:38 AM
(premap)Complete 5 122 0 0m:05s 0m:06s 206MB 10/9/2023
9:38 AM
(fpga_mapper)Complete 9 5 0 0m:22s 0m:30s 228MB 10/9/2023
9:38 AM
Multi-srs Generator Complete00m:03s10/9/2023
9:38 AM

Area Summary
Register bits 945 I/O cells 6
Block RAMs (v_ram) 2 DSPs (dsp_used) 0
LUTs (total_luts) 925

Timing Summary
Clock NameReq FreqEst FreqSlack
Top|clk1501.0 MHz259.5 MHz996.146
Top|jtck_inferred_clock1.0 MHz180.3 MHz994.453
rvltck30.0 MHzNANA
System1.0 MHz382.0 MHz997.383

Optimizations Summary
Combined Clock Conversion 2 / 0