Project Settings
Project Name proj_1 Device Name impl1: Lattice LFCPNX : LFCPNX_100
Implementation Name impl1 Top Module Top
Pipelining 1 Retiming 0
Resource Sharing 1 Fanout Guide 1000
Disable I/O Insertion 0 Disable Sequential Optimizations 0
Clock Conversion 0 FSM Compiler 1

Run Status
Job Name Status CPU Time Real Time Memory Date/Time
(compiler)Complete 81 0 0 - 00m:01s - 2023-12-01
10:23 AM
(premap)Complete 5 0 0 0m:00s 0m:01s 198MB 2023-12-01
10:23 AM
(fpga_mapper)Complete 10 0 0 0m:01s 0m:02s 201MB 2023-12-01
10:23 AM
Multi-srs Generator Complete2023-12-01
10:23 AM

Area Summary
Register bits 38 I/O cells 6
Block RAMs (v_ram) 0 DSPs (dsp_used) 0
LUTs (total_luts) 2

Timing Summary
Clock NameReq FreqEst FreqSlack
CLK1150.0 MHz400.4 MHz4.169
clk2150.0 MHz400.4 MHz4.169
System1.0 MHzNANA

Optimizations Summary
Combined Clock Conversion 2 / 0