Timing Report
Lattice Timing Report - Setup and Hold, Version Radiant Software (64-bit) 2023.2.0.38.1
Thu Dec 21 16:42:40 2023
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2023 Lattice Semiconductor Corporation, All rights reserved.
Command line: timing -sethld -v 10 -u 10 -endpoints 10 -nperend 1 -sp 9_High-Performance_1.0V -hsp m -pwrprd -html -rpt LAB03_Async_rst.twr LAB03_Async_rst.udb -gui -msgset D:/02_LSCC/09_GSR/Final/LAB03_Sync_rst/promote.xml
-------------------------------------------
Design: Top
Family: LFCPNX
Device: LFCPNX-100
Package: LFG672
Performance: 9_High-Performance_1.0V
Package Status: Final Version 16
Performance Hardware Data Status : Final Version 3.9
-------------------------------------------
=====================================================================
Table of Contents
=====================================================================
1 Timing Overview
1.1 SDC Constraints
1.2 Constraint Coverage
1.3 Overall Summary
1.4 Unconstrained Report
1.5 Combinational Loop
2 Setup at Speed Grade 9_High-Performance_1.0V Corner at 85 Degrees
2.1 Clock Summary
2.2 Endpoint slacks
2.3 Detailed Report
3 Setup at Speed Grade 9_High-Performance_1.0V Corner at 0 Degrees
3.1 Clock Summary
3.2 Endpoint slacks
3.3 Detailed Report
4 Hold at Speed Grade m Corner at 0 Degrees
4.1 Endpoint slacks
4.2 Detailed Report
=====================================================================
End of Table of Contents
=====================================================================
1 Timing Overview
1.1 SDC Constraints
create_clock -name {clk150} -period 8.88889 [get_pins {OSCA001.OSCA_inst/HFCLKOUT }]
create_clock -name {rvltck} -period 33.33 [get_ports TCK]
set_false_path -to [get_clocks rvltck]
set_false_path -from [get_clocks rvltck]
set_clock_groups -group [get_clocks clk150] -group [get_clocks rvltck] -asynchronous
1.2 Constraint Coverage
Constraint Coverage: 95.2149%
1.3 Overall Summary
Setup at Speed Grade 9_High-Performance_1.0V Corner at 85 Degrees Timing Errors: 0 endpoints; Total Negative Slack: 0.000 ns
Setup at Speed Grade 9_High-Performance_1.0V Corner at 0 Degrees Timing Errors: 0 endpoints; Total Negative Slack: 0.000 ns
Hold at Speed Grade m Corner at 0 Degrees Timing Errors: 0 endpoints; Total Negative Slack: 0.000 ns
1.4 Unconstrained Report
1.4.1 Unconstrained Start/End Points
Clocked but unconstrained timing start points
-------------------------------------------------------------------
Listing 4 Start Points | Type
-------------------------------------------------------------------
LED4_0io.PIC_inst/Q | No required time
LED3_0io.PIC_inst/Q | No required time
LED2_0io.PIC_inst/Q | No required time
LED1_0io.PIC_inst/Q | No required time
-------------------------------------------------------------------
|
Number of unconstrained timing start po |
ints | 4
|
-------------------------------------------------------------------
Clocked but unconstrained timing end points
-------------------------------------------------------------------
Listing 5 End Points | Type
-------------------------------------------------------------------
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_269/DF
| No arrival or required
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_273/DF
| No arrival or required
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_272/DF
| No arrival or required
top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_465/DF
| No arrival or required
rsti_0io.PIC_inst/D | No arrival time
-------------------------------------------------------------------
|
Number of unconstrained timing end poin |
ts | 5
|
-------------------------------------------------------------------
1.4.2 Start/End Points Without Timing Constraints
I/O ports without constraint
----------------------------
Possible constraints to use on I/O ports are:
set_input_delay,
set_output_delay,
set_max_delay,
create_clock,
create_generated_clock,
...
-------------------------------------------------------------------
Listing 6 Start or End Points | Type
-------------------------------------------------------------------
en | input
reset | input
LED4 | output
LED3 | output
LED2 | output
LED1 | output
-------------------------------------------------------------------
|
Number of I/O ports without constraint | 6
|
-------------------------------------------------------------------
Nets without clock definition
Define a clock on a top level port or a generated clock on a clock divider pin associated with this net(s).
--------------------------------------------------
There is no instance satisfying reporting criteria
1.5 Combinational Loop
None
2 Setup at Speed Grade 9_High-Performance_1.0V Corner at 85 Degrees
2.1 Clock Summary
2.1.1 Clock "clk150"
create_clock -name {clk150} -period 8.88889 [get_pins {OSCA001.OSCA_inst/HFCLKOUT }]
Single Clock Domain
-------------------------------------------------------------------------------------------------------
Clock clk150 | | Period | Frequency
-------------------------------------------------------------------------------------------------------
From clk150 | Target | 8.889 ns | 112.500 MHz
| Actual (all paths) | 5.744 ns | 174.095 MHz
OSCA001.OSCA_inst/HFCLKOUT (MPW) | (50% duty cycle) | 4.354 ns | 229.674 MHz
-------------------------------------------------------------------------------------------------------
Clock Domain Crossing
------------------------------------------------------------------------------------------------------
Clock clk150 | Worst Time Between Edges | Comment
------------------------------------------------------------------------------------------------------
From rvltck | ---- | False path
------------------------------------------------------------------------------------------------------
2.1.2 Clock "rvltck"
create_clock -name {rvltck} -period 33.33 [get_ports TCK]
Single Clock Domain
-------------------------------------------------------------------------------------------------------
Clock rvltck | | Period | Frequency
-------------------------------------------------------------------------------------------------------
From rvltck | Target | 33.330 ns | 30.003 MHz
| Actual (all paths) | 5.000 ns | 200.000 MHz
jtaghub_inst/IB_inst2.bb_inst/B (MPW) | (50% duty cycle) | 5.000 ns | 200.000 MHz
-------------------------------------------------------------------------------------------------------
Clock Domain Crossing
------------------------------------------------------------------------------------------------------
Clock rvltck | Worst Time Between Edges | Comment
------------------------------------------------------------------------------------------------------
From clk150 | ---- | False path
------------------------------------------------------------------------------------------------------
2.2 Endpoint slacks
-------------------------------------------------------
Listing 10 End Points | Slack
-------------------------------------------------------
LED3_0io.PIC_inst/D | 3.145 ns
LED1_0io.PIC_inst/D | 3.237 ns
{top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_103/CE top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_104/CE}
| 3.314 ns
CNT03/Couti_reg[0].ff_inst/LSR | 3.412 ns
{CNT03/Couti_reg[1].ff_inst/LSR CNT03/Couti_reg[2].ff_inst/LSR}
| 3.412 ns
{CNT03/Couti_reg[3].ff_inst/LSR CNT03/Couti_reg[4].ff_inst/LSR}
| 3.412 ns
{CNT03/Couti_reg[5].ff_inst/LSR CNT03/Couti_reg[6].ff_inst/LSR}
| 3.412 ns
{CNT03/Couti_reg[11].ff_inst/LSR CNT03/Couti_reg[12].ff_inst/LSR}
| 3.528 ns
{CNT03/Couti_reg[13].ff_inst/LSR CNT03/Couti_reg[14].ff_inst/LSR}
| 3.528 ns
CNT03/Couti_reg[15].ff_inst/LSR | 3.528 ns
-------------------------------------------------------
|
Setup # of endpoints with negative slack:| 0
|
-------------------------------------------------------
2.3 Detailed Report
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
Detail report of critical paths
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Detailed Report for timing paths
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++++Path 1 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : CNT03/Couti_reg[15].ff_inst/Q (SLICE_R60C11A)
Path End : LED3_0io.PIC_inst/D (SIOLOGIC_CORE_IOL_R31A)
Source Clock : clk150 (R)
Destination Clock: clk150 (R)
Logic Level : 2
Delay Ratio : 90.8% (route), 9.2% (logic)
Clock Skew : -0.086 ns
Setup Constraint : 8.888 ns
Common Path Skew : 0.028 ns
Path Slack : 3.144 ns (Passed)
Source Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"CNT03/Couti_reg[15].ff_inst/CLK",
"phy_name":"CNT03.SLICE_128/CLK"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":2.367,
"delay":2.367
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":2.367,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 331
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141
NET DELAY 2.367 2.367 331
CNT03/Couti_reg[15].ff_inst/CLK CLOCK PIN 0.000 2.367 1
Data Path
{
"path_begin":
{
"type":"pin",
"log_name":"CNT03/Couti_reg[15].ff_inst/Q",
"phy_name":"CNT03.SLICE_128/Q0"
},
"path_end":
{
"type":"pin",
"log_name":"LED3_0io.PIC_inst/D",
"phy_name":"LED3_pad.bb_inst_IOL/TXDATA0"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"CNT03/Couti_reg[15].ff_inst/CLK",
"phy_name":"CNT03.SLICE_128/CLK"
},
"pin1":
{
"log_name":"CNT03/Couti_reg[15].ff_inst/Q",
"phy_name":"CNT03.SLICE_128/Q0"
},
"arrive":2.659,
"delay":0.292
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_signal_1_57",
"phy_name":"CNT3[15]"
},
"arrive":5.185,
"delay":2.526
},
{
"type":"site_delay",
"pin0":
{
"log_name":"LED3_1_cZ/B",
"phy_name":"SLICE_1030/B1"
},
"pin1":
{
"log_name":"LED3_1_cZ/Z",
"phy_name":"SLICE_1030/F1"
},
"arrive":5.390,
"delay":0.205
},
{
"type":"net_delay",
"net":
{
"log_name":"LED3_1",
"phy_name":"LED3_1"
},
"arrive":7.759,
"delay":2.369
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":7.759,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
CNT03/Couti_reg[15].ff_inst/CLK->CNT03/Couti_reg[15].ff_inst/Q
SLICE_R60C11A REG_DEL 0.292 2.659 4
top_reveal_coretop_instance/core0/tm_u/secured_signal_1_57
NET DELAY 2.526 5.185 4
LED3_1_cZ/B->LED3_1_cZ/Z SLICE_R35C78B CTOF_DEL 0.205 5.390 1
LED3_1 NET DELAY 2.369 7.759 1
LED3_0io.PIC_inst/D ENDPOINT 0.000 7.759 1
Destination Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"LED3_0io.PIC_inst/CLK",
"phy_name":"LED3_pad.bb_inst_IOL/SCLKOUT"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":8.888,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":11.169,
"delay":2.281
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":11.169,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
CONSTRAINT 0.000 8.888 1
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 8.888 331
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141
NET DELAY 2.281 11.169 331
LED3_0io.PIC_inst/CLK CLOCK PIN 0.000 11.169 1
Uncertainty -(0.000) 11.169
Common Path Skew 0.028 11.197
Setup time -(0.294) 10.903
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
Required Time 10.903
Arrival Time -(7.758)
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
Path Slack (Passed) 3.144
++++ Path 2 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : CNT01/Couti_reg[15].ff_inst/Q (SLICE_R14C14A)
Path End : LED1_0io.PIC_inst/D (SIOLOGIC_CORE_IOL_R28B)
Source Clock : clk150 (R)
Destination Clock: clk150 (R)
Logic Level : 2
Delay Ratio : 90.6% (route), 9.4% (logic)
Clock Skew : -0.086 ns
Setup Constraint : 8.888 ns
Common Path Skew : 0.028 ns
Path Slack : 3.236 ns (Passed)
Source Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"CNT01/Couti_reg[15].ff_inst/CLK",
"phy_name":"CNT01.SLICE_110/CLK"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":2.367,
"delay":2.367
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":2.367,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 331
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141
NET DELAY 2.367 2.367 331
CNT01/Couti_reg[15].ff_inst/CLK CLOCK PIN 0.000 2.367 1
Data Path
{
"path_begin":
{
"type":"pin",
"log_name":"CNT01/Couti_reg[15].ff_inst/Q",
"phy_name":"CNT01.SLICE_110/Q0"
},
"path_end":
{
"type":"pin",
"log_name":"LED1_0io.PIC_inst/D",
"phy_name":"LED1_pad.bb_inst_IOL/TXDATA0"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"CNT01/Couti_reg[15].ff_inst/CLK",
"phy_name":"CNT01.SLICE_110/CLK"
},
"pin1":
{
"log_name":"CNT01/Couti_reg[15].ff_inst/Q",
"phy_name":"CNT01.SLICE_110/Q0"
},
"arrive":2.659,
"delay":0.292
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_signal_1_25",
"phy_name":"CNT1[15]"
},
"arrive":5.002,
"delay":2.343
},
{
"type":"site_delay",
"pin0":
{
"log_name":"LED1_1_cZ/B",
"phy_name":"SLICE_1028/B1"
},
"pin1":
{
"log_name":"LED1_1_cZ/Z",
"phy_name":"SLICE_1028/F1"
},
"arrive":5.207,
"delay":0.205
},
{
"type":"net_delay",
"net":
{
"log_name":"LED1_1",
"phy_name":"LED1_1"
},
"arrive":7.667,
"delay":2.460
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":7.667,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
CNT01/Couti_reg[15].ff_inst/CLK->CNT01/Couti_reg[15].ff_inst/Q
SLICE_R14C14A REG_DEL 0.292 2.659 4
top_reveal_coretop_instance/core0/tm_u/secured_signal_1_25
NET DELAY 2.343 5.002 4
LED1_1_cZ/B->LED1_1_cZ/Z SLICE_R33C79D CTOF_DEL 0.205 5.207 1
LED1_1 NET DELAY 2.460 7.667 1
LED1_0io.PIC_inst/D ENDPOINT 0.000 7.667 1
Destination Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"LED1_0io.PIC_inst/CLK",
"phy_name":"LED1_pad.bb_inst_IOL/SCLKOUT"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":8.888,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":11.169,
"delay":2.281
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":11.169,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
CONSTRAINT 0.000 8.888 1
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 8.888 331
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141
NET DELAY 2.281 11.169 331
LED1_0io.PIC_inst/CLK CLOCK PIN 0.000 11.169 1
Uncertainty -(0.000) 11.169
Common Path Skew 0.028 11.197
Setup time -(0.294) 10.903
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
Required Time 10.903
Arrival Time -(7.666)
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
Path Slack (Passed) 3.236
++++ Path 3 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_468/Q (SLICE_R36C82B)
Path End : {top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_103/CE top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_104/CE} (SLICE_R43C72B)
Source Clock : clk150 (R)
Destination Clock: clk150 (R)
Logic Level : 7
Delay Ratio : 70.3% (route), 29.7% (logic)
Clock Skew : -0.132 ns
Setup Constraint : 8.888 ns
Common Path Skew : 0.028 ns
Path Slack : 3.313 ns (Passed)
Source Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_467/CLK",
"phy_name":"top_reveal_coretop_instance.core0.jtag_int_u.SLICE_1248/CLK"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":2.367,
"delay":2.367
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":2.367,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 331
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141
NET DELAY 2.367 2.367 331
{top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_467/CLK top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_468/CLK}
CLOCK PIN 0.000 2.367 1
Data Path
{
"path_begin":
{
"type":"pin",
"log_name":"top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_468/Q",
"phy_name":"top_reveal_coretop_instance.core0.jtag_int_u.SLICE_1248/Q1"
},
"path_end":
{
"type":"pin",
"log_name":"{top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_103/CE top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_104/CE}",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tu_3.IhL6rK7kjDdr78xjJ[4].SLICE_824/CE"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_468/CLK",
"phy_name":"top_reveal_coretop_instance.core0.jtag_int_u.SLICE_1248/CLK"
},
"pin1":
{
"log_name":"top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_468/Q",
"phy_name":"top_reveal_coretop_instance.core0.jtag_int_u.SLICE_1248/Q1"
},
"arrive":2.674,
"delay":0.307
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/jtag_int_u/secured_signal_2_155",
"phy_name":"top_reveal_coretop_instance.core0.jtag_int_u.Ne3nFILyd5q303pD9C8l[3]"
},
"arrive":3.085,
"delay":0.411
},
{
"type":"site_delay",
"pin0":
{
"log_name":"top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_243/B",
"phy_name":"top_reveal_coretop_instance.core0.jtag_int_u.SLICE_1248/C0"
},
"pin1":
{
"log_name":"top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_243/Z",
"phy_name":"top_reveal_coretop_instance.core0.jtag_int_u.SLICE_1248/F0"
},
"arrive":3.290,
"delay":0.205
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/jtag_int_u/secured_signal_2_577",
"phy_name":"top_reveal_coretop_instance.core0.jtag_int_u.Nb4zmjgl42aqur7c"
},
"arrive":3.725,
"delay":0.435
},
{
"type":"site_delay",
"pin0":
{
"log_name":"top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_233/D",
"phy_name":"top_reveal_coretop_instance.core0.jtag_int_u.SLICE_1241/B1"
},
"pin1":
{
"log_name":"top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_233/Z",
"phy_name":"top_reveal_coretop_instance.core0.jtag_int_u.SLICE_1241/F1"
},
"arrive":3.938,
"delay":0.213
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_signal_1_157",
"phy_name":"top_reveal_coretop_instance.core0.wen"
},
"arrive":4.505,
"delay":0.567
},
{
"type":"site_delay",
"pin0":
{
"log_name":"top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_15_17/B",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.decode_u.SLICE_1756/C1"
},
"pin1":
{
"log_name":"top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_15_17/Z",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.decode_u.SLICE_1756/F1"
},
"arrive":4.718,
"delay":0.213
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/trig_u/decode_u/secured_signal_15_26",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.decode_u.Nfh7o1A"
},
"arrive":5.010,
"delay":0.292
},
{
"type":"site_delay",
"pin0":
{
"log_name":"top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_15_6/A",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.decode_u.SLICE_1748/A1"
},
"pin1":
{
"log_name":"top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_15_6/Z",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.decode_u.SLICE_1748/F1"
},
"arrive":5.215,
"delay":0.205
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/trig_u/decode_u/secured_signal_15_28",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.decode_u.Nfh7o1E"
},
"arrive":5.854,
"delay":0.639
},
{
"type":"site_delay",
"pin0":
{
"log_name":"top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_15_3/A",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tu_3.SLICE_1518/B1"
},
"pin1":
{
"log_name":"top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_15_3/Z",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tu_3.SLICE_1518/F1"
},
"arrive":6.067,
"delay":0.213
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/trig_u/tu_3/secured_signal_11_56",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.wen_tu[3]"
},
"arrive":6.348,
"delay":0.281
},
{
"type":"site_delay",
"pin0":
{
"log_name":"top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_5/C",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tu_3.SLICE_1517/A0"
},
"pin1":
{
"log_name":"top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_5/Z",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tu_3.SLICE_1517/F0"
},
"arrive":6.561,
"delay":0.213
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/trig_u/tu_3/secured_signal_11_149",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tu_3.NfmqpHfyLjihmE893lg93s3sdHIgm7"
},
"arrive":7.645,
"delay":1.084
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":7.645,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_468/CLK->top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_468/Q
SLICE_R36C82B REG_DEL 0.307 2.674 4
top_reveal_coretop_instance/core0/jtag_int_u/secured_signal_2_155
NET DELAY 0.411 3.085 4
top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_243/B->top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_243/Z
SLICE_R36C82B CTOF_DEL 0.205 3.290 1
top_reveal_coretop_instance/core0/jtag_int_u/secured_signal_2_577
NET DELAY 0.435 3.725 1
top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_233/D->top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_233/Z
SLICE_R38C81B CTOF_DEL 0.213 3.938 5
top_reveal_coretop_instance/core0/tm_u/secured_signal_1_157
NET DELAY 0.567 4.505 5
top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_15_17/B->top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_15_17/Z
SLICE_R32C78B CTOF_DEL 0.213 4.718 3
top_reveal_coretop_instance/core0/trig_u/decode_u/secured_signal_15_26
NET DELAY 0.292 5.010 3
top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_15_6/A->top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_15_6/Z
SLICE_R33C78A CTOF_DEL 0.205 5.215 3
top_reveal_coretop_instance/core0/trig_u/decode_u/secured_signal_15_28
NET DELAY 0.639 5.854 3
top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_15_3/A->top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_15_3/Z
SLICE_R36C82C CTOF_DEL 0.213 6.067 3
top_reveal_coretop_instance/core0/trig_u/tu_3/secured_signal_11_56
NET DELAY 0.281 6.348 3
top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_5/C->top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_5/Z
SLICE_R36C83C CTOF_DEL 0.213 6.561 8
top_reveal_coretop_instance/core0/trig_u/tu_3/secured_signal_11_149
NET DELAY 1.084 7.645 8
{top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_103/CE top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_104/CE}
ENDPOINT 0.000 7.645 1
Destination Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_103/CLK",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tu_3.IhL6rK7kjDdr78xjJ[4].SLICE_824/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":8.888,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":11.123,
"delay":2.235
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":11.123,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
CONSTRAINT 0.000 8.888 1
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 8.888 331
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141
NET DELAY 2.235 11.123 331
{top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_103/CLK top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_104/CLK}
CLOCK PIN 0.000 11.123 1
Uncertainty -(0.000) 11.123
Common Path Skew 0.028 11.151
Setup time -(0.193) 10.958
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
Required Time 10.958
Arrival Time -(7.644)
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
Path Slack (Passed) 3.313
++++ Path 4 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : rsti_0io.PIC_inst/Q (SIOLOGIC_CORE_IOL_R24A)
Path End : CNT03/Couti_reg[0].ff_inst/LSR (SLICE_R60C9A)
Source Clock : clk150 (R)
Destination Clock: clk150 (R)
Logic Level : 1
Delay Ratio : 91.8% (route), 8.2% (logic)
Clock Skew : -0.216 ns
Setup Constraint : 8.888 ns
Common Path Skew : 0.028 ns
Path Slack : 3.411 ns (Passed)
Source Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"rsti_0io.PIC_inst/CLK",
"phy_name":"reset_pad.bb_inst_IOL/SCLKIN"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":2.451,
"delay":2.451
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":2.451,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 331
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141
NET DELAY 2.451 2.451 331
rsti_0io.PIC_inst/CLK CLOCK PIN 0.000 2.451 1
Data Path
{
"path_begin":
{
"type":"pin",
"log_name":"rsti_0io.PIC_inst/Q",
"phy_name":"reset_pad.bb_inst_IOL/INFF"
},
"path_end":
{
"type":"pin",
"log_name":"CNT03/Couti_reg[0].ff_inst/LSR",
"phy_name":"CNT03.SLICE_136/LSR"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"rsti_0io.PIC_inst/CLK",
"phy_name":"reset_pad.bb_inst_IOL/SCLKIN"
},
"pin1":
{
"log_name":"rsti_0io.PIC_inst/Q",
"phy_name":"reset_pad.bb_inst_IOL/INFF"
},
"arrive":2.867,
"delay":0.416
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_signal_1_89",
"phy_name":"rsti_1"
},
"arrive":7.543,
"delay":4.676
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":7.543,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
rsti_0io.PIC_inst/CLK->rsti_0io.PIC_inst/Q
SIOLOGIC_CORE_IOL_R24A C2INP_DEL 0.416 2.867 38
top_reveal_coretop_instance/core0/tm_u/secured_signal_1_89
NET DELAY 4.676 7.543 38
CNT03/Couti_reg[0].ff_inst/LSR ENDPOINT 0.000 7.543 1
Destination Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"CNT03/Couti_reg[0].ff_inst/CLK",
"phy_name":"CNT03.SLICE_136/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":8.888,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":11.123,
"delay":2.235
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":11.123,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
CONSTRAINT 0.000 8.888 1
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 8.888 331
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141
NET DELAY 2.235 11.123 331
CNT03/Couti_reg[0].ff_inst/CLK CLOCK PIN 0.000 11.123 1
Uncertainty -(0.000) 11.123
Common Path Skew 0.028 11.151
Setup time -(0.197) 10.954
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
Required Time 10.954
Arrival Time -(7.542)
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
Path Slack (Passed) 3.411
++++ Path 5 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : rsti_0io.PIC_inst/Q (SIOLOGIC_CORE_IOL_R24A)
Path End : {CNT03/Couti_reg[1].ff_inst/LSR CNT03/Couti_reg[2].ff_inst/LSR} (SLICE_R60C9B)
Source Clock : clk150 (R)
Destination Clock: clk150 (R)
Logic Level : 1
Delay Ratio : 91.8% (route), 8.2% (logic)
Clock Skew : -0.216 ns
Setup Constraint : 8.888 ns
Common Path Skew : 0.028 ns
Path Slack : 3.411 ns (Passed)
Source Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"rsti_0io.PIC_inst/CLK",
"phy_name":"reset_pad.bb_inst_IOL/SCLKIN"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":2.451,
"delay":2.451
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":2.451,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 331
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141
NET DELAY 2.451 2.451 331
rsti_0io.PIC_inst/CLK CLOCK PIN 0.000 2.451 1
Data Path
{
"path_begin":
{
"type":"pin",
"log_name":"rsti_0io.PIC_inst/Q",
"phy_name":"reset_pad.bb_inst_IOL/INFF"
},
"path_end":
{
"type":"pin",
"log_name":"{CNT03/Couti_reg[1].ff_inst/LSR CNT03/Couti_reg[2].ff_inst/LSR}",
"phy_name":"CNT03.SLICE_135/LSR"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"rsti_0io.PIC_inst/CLK",
"phy_name":"reset_pad.bb_inst_IOL/SCLKIN"
},
"pin1":
{
"log_name":"rsti_0io.PIC_inst/Q",
"phy_name":"reset_pad.bb_inst_IOL/INFF"
},
"arrive":2.867,
"delay":0.416
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_signal_1_89",
"phy_name":"rsti_1"
},
"arrive":7.543,
"delay":4.676
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":7.543,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
rsti_0io.PIC_inst/CLK->rsti_0io.PIC_inst/Q
SIOLOGIC_CORE_IOL_R24A C2INP_DEL 0.416 2.867 38
top_reveal_coretop_instance/core0/tm_u/secured_signal_1_89
NET DELAY 4.676 7.543 38
{CNT03/Couti_reg[1].ff_inst/LSR CNT03/Couti_reg[2].ff_inst/LSR}
ENDPOINT 0.000 7.543 1
Destination Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"CNT03/Couti_reg[1].ff_inst/CLK",
"phy_name":"CNT03.SLICE_135/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":8.888,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":11.123,
"delay":2.235
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":11.123,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
CONSTRAINT 0.000 8.888 1
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 8.888 331
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141
NET DELAY 2.235 11.123 331
{CNT03/Couti_reg[1].ff_inst/CLK CNT03/Couti_reg[2].ff_inst/CLK}
CLOCK PIN 0.000 11.123 1
Uncertainty -(0.000) 11.123
Common Path Skew 0.028 11.151
Setup time -(0.197) 10.954
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
Required Time 10.954
Arrival Time -(7.542)
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
Path Slack (Passed) 3.411
++++ Path 6 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : rsti_0io.PIC_inst/Q (SIOLOGIC_CORE_IOL_R24A)
Path End : {CNT03/Couti_reg[3].ff_inst/LSR CNT03/Couti_reg[4].ff_inst/LSR} (SLICE_R60C9C)
Source Clock : clk150 (R)
Destination Clock: clk150 (R)
Logic Level : 1
Delay Ratio : 91.8% (route), 8.2% (logic)
Clock Skew : -0.216 ns
Setup Constraint : 8.888 ns
Common Path Skew : 0.028 ns
Path Slack : 3.411 ns (Passed)
Source Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"rsti_0io.PIC_inst/CLK",
"phy_name":"reset_pad.bb_inst_IOL/SCLKIN"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":2.451,
"delay":2.451
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":2.451,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 331
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141
NET DELAY 2.451 2.451 331
rsti_0io.PIC_inst/CLK CLOCK PIN 0.000 2.451 1
Data Path
{
"path_begin":
{
"type":"pin",
"log_name":"rsti_0io.PIC_inst/Q",
"phy_name":"reset_pad.bb_inst_IOL/INFF"
},
"path_end":
{
"type":"pin",
"log_name":"{CNT03/Couti_reg[3].ff_inst/LSR CNT03/Couti_reg[4].ff_inst/LSR}",
"phy_name":"CNT03.SLICE_134/LSR"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"rsti_0io.PIC_inst/CLK",
"phy_name":"reset_pad.bb_inst_IOL/SCLKIN"
},
"pin1":
{
"log_name":"rsti_0io.PIC_inst/Q",
"phy_name":"reset_pad.bb_inst_IOL/INFF"
},
"arrive":2.867,
"delay":0.416
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_signal_1_89",
"phy_name":"rsti_1"
},
"arrive":7.543,
"delay":4.676
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":7.543,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
rsti_0io.PIC_inst/CLK->rsti_0io.PIC_inst/Q
SIOLOGIC_CORE_IOL_R24A C2INP_DEL 0.416 2.867 38
top_reveal_coretop_instance/core0/tm_u/secured_signal_1_89
NET DELAY 4.676 7.543 38
{CNT03/Couti_reg[3].ff_inst/LSR CNT03/Couti_reg[4].ff_inst/LSR}
ENDPOINT 0.000 7.543 1
Destination Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"CNT03/Couti_reg[3].ff_inst/CLK",
"phy_name":"CNT03.SLICE_134/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":8.888,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":11.123,
"delay":2.235
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":11.123,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
CONSTRAINT 0.000 8.888 1
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 8.888 331
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141
NET DELAY 2.235 11.123 331
{CNT03/Couti_reg[3].ff_inst/CLK CNT03/Couti_reg[4].ff_inst/CLK}
CLOCK PIN 0.000 11.123 1
Uncertainty -(0.000) 11.123
Common Path Skew 0.028 11.151
Setup time -(0.197) 10.954
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
Required Time 10.954
Arrival Time -(7.542)
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
Path Slack (Passed) 3.411
++++ Path 7 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : rsti_0io.PIC_inst/Q (SIOLOGIC_CORE_IOL_R24A)
Path End : {CNT03/Couti_reg[5].ff_inst/LSR CNT03/Couti_reg[6].ff_inst/LSR} (SLICE_R60C9D)
Source Clock : clk150 (R)
Destination Clock: clk150 (R)
Logic Level : 1
Delay Ratio : 91.8% (route), 8.2% (logic)
Clock Skew : -0.216 ns
Setup Constraint : 8.888 ns
Common Path Skew : 0.028 ns
Path Slack : 3.411 ns (Passed)
Source Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"rsti_0io.PIC_inst/CLK",
"phy_name":"reset_pad.bb_inst_IOL/SCLKIN"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":2.451,
"delay":2.451
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":2.451,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 331
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141
NET DELAY 2.451 2.451 331
rsti_0io.PIC_inst/CLK CLOCK PIN 0.000 2.451 1
Data Path
{
"path_begin":
{
"type":"pin",
"log_name":"rsti_0io.PIC_inst/Q",
"phy_name":"reset_pad.bb_inst_IOL/INFF"
},
"path_end":
{
"type":"pin",
"log_name":"{CNT03/Couti_reg[5].ff_inst/LSR CNT03/Couti_reg[6].ff_inst/LSR}",
"phy_name":"CNT03.SLICE_133/LSR"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"rsti_0io.PIC_inst/CLK",
"phy_name":"reset_pad.bb_inst_IOL/SCLKIN"
},
"pin1":
{
"log_name":"rsti_0io.PIC_inst/Q",
"phy_name":"reset_pad.bb_inst_IOL/INFF"
},
"arrive":2.867,
"delay":0.416
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_signal_1_89",
"phy_name":"rsti_1"
},
"arrive":7.543,
"delay":4.676
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":7.543,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
rsti_0io.PIC_inst/CLK->rsti_0io.PIC_inst/Q
SIOLOGIC_CORE_IOL_R24A C2INP_DEL 0.416 2.867 38
top_reveal_coretop_instance/core0/tm_u/secured_signal_1_89
NET DELAY 4.676 7.543 38
{CNT03/Couti_reg[5].ff_inst/LSR CNT03/Couti_reg[6].ff_inst/LSR}
ENDPOINT 0.000 7.543 1
Destination Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"CNT03/Couti_reg[5].ff_inst/CLK",
"phy_name":"CNT03.SLICE_133/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":8.888,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":11.123,
"delay":2.235
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":11.123,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
CONSTRAINT 0.000 8.888 1
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 8.888 331
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141
NET DELAY 2.235 11.123 331
{CNT03/Couti_reg[5].ff_inst/CLK CNT03/Couti_reg[6].ff_inst/CLK}
CLOCK PIN 0.000 11.123 1
Uncertainty -(0.000) 11.123
Common Path Skew 0.028 11.151
Setup time -(0.197) 10.954
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
Required Time 10.954
Arrival Time -(7.542)
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
Path Slack (Passed) 3.411
++++ Path 8 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : rsti_0io.PIC_inst/Q (SIOLOGIC_CORE_IOL_R24A)
Path End : {CNT03/Couti_reg[11].ff_inst/LSR CNT03/Couti_reg[12].ff_inst/LSR} (SLICE_R60C10C)
Source Clock : clk150 (R)
Destination Clock: clk150 (R)
Logic Level : 1
Delay Ratio : 91.6% (route), 8.4% (logic)
Clock Skew : -0.216 ns
Setup Constraint : 8.888 ns
Common Path Skew : 0.028 ns
Path Slack : 3.527 ns (Passed)
Source Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"rsti_0io.PIC_inst/CLK",
"phy_name":"reset_pad.bb_inst_IOL/SCLKIN"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":2.451,
"delay":2.451
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":2.451,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 331
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141
NET DELAY 2.451 2.451 331
rsti_0io.PIC_inst/CLK CLOCK PIN 0.000 2.451 1
Data Path
{
"path_begin":
{
"type":"pin",
"log_name":"rsti_0io.PIC_inst/Q",
"phy_name":"reset_pad.bb_inst_IOL/INFF"
},
"path_end":
{
"type":"pin",
"log_name":"{CNT03/Couti_reg[11].ff_inst/LSR CNT03/Couti_reg[12].ff_inst/LSR}",
"phy_name":"CNT03.SLICE_130/LSR"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"rsti_0io.PIC_inst/CLK",
"phy_name":"reset_pad.bb_inst_IOL/SCLKIN"
},
"pin1":
{
"log_name":"rsti_0io.PIC_inst/Q",
"phy_name":"reset_pad.bb_inst_IOL/INFF"
},
"arrive":2.867,
"delay":0.416
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_signal_1_89",
"phy_name":"rsti_1"
},
"arrive":7.427,
"delay":4.560
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":7.427,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
rsti_0io.PIC_inst/CLK->rsti_0io.PIC_inst/Q
SIOLOGIC_CORE_IOL_R24A C2INP_DEL 0.416 2.867 38
top_reveal_coretop_instance/core0/tm_u/secured_signal_1_89
NET DELAY 4.560 7.427 38
{CNT03/Couti_reg[11].ff_inst/LSR CNT03/Couti_reg[12].ff_inst/LSR}
ENDPOINT 0.000 7.427 1
Destination Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"CNT03/Couti_reg[11].ff_inst/CLK",
"phy_name":"CNT03.SLICE_130/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":8.888,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":11.123,
"delay":2.235
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":11.123,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
CONSTRAINT 0.000 8.888 1
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 8.888 331
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141
NET DELAY 2.235 11.123 331
{CNT03/Couti_reg[11].ff_inst/CLK CNT03/Couti_reg[12].ff_inst/CLK}
CLOCK PIN 0.000 11.123 1
Uncertainty -(0.000) 11.123
Common Path Skew 0.028 11.151
Setup time -(0.197) 10.954
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
Required Time 10.954
Arrival Time -(7.426)
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
Path Slack (Passed) 3.527
++++ Path 9 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : rsti_0io.PIC_inst/Q (SIOLOGIC_CORE_IOL_R24A)
Path End : {CNT03/Couti_reg[13].ff_inst/LSR CNT03/Couti_reg[14].ff_inst/LSR} (SLICE_R60C10D)
Source Clock : clk150 (R)
Destination Clock: clk150 (R)
Logic Level : 1
Delay Ratio : 91.6% (route), 8.4% (logic)
Clock Skew : -0.216 ns
Setup Constraint : 8.888 ns
Common Path Skew : 0.028 ns
Path Slack : 3.527 ns (Passed)
Source Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"rsti_0io.PIC_inst/CLK",
"phy_name":"reset_pad.bb_inst_IOL/SCLKIN"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":2.451,
"delay":2.451
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":2.451,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 331
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141
NET DELAY 2.451 2.451 331
rsti_0io.PIC_inst/CLK CLOCK PIN 0.000 2.451 1
Data Path
{
"path_begin":
{
"type":"pin",
"log_name":"rsti_0io.PIC_inst/Q",
"phy_name":"reset_pad.bb_inst_IOL/INFF"
},
"path_end":
{
"type":"pin",
"log_name":"{CNT03/Couti_reg[13].ff_inst/LSR CNT03/Couti_reg[14].ff_inst/LSR}",
"phy_name":"CNT03.SLICE_129/LSR"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"rsti_0io.PIC_inst/CLK",
"phy_name":"reset_pad.bb_inst_IOL/SCLKIN"
},
"pin1":
{
"log_name":"rsti_0io.PIC_inst/Q",
"phy_name":"reset_pad.bb_inst_IOL/INFF"
},
"arrive":2.867,
"delay":0.416
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_signal_1_89",
"phy_name":"rsti_1"
},
"arrive":7.427,
"delay":4.560
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":7.427,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
rsti_0io.PIC_inst/CLK->rsti_0io.PIC_inst/Q
SIOLOGIC_CORE_IOL_R24A C2INP_DEL 0.416 2.867 38
top_reveal_coretop_instance/core0/tm_u/secured_signal_1_89
NET DELAY 4.560 7.427 38
{CNT03/Couti_reg[13].ff_inst/LSR CNT03/Couti_reg[14].ff_inst/LSR}
ENDPOINT 0.000 7.427 1
Destination Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"CNT03/Couti_reg[13].ff_inst/CLK",
"phy_name":"CNT03.SLICE_129/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":8.888,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":11.123,
"delay":2.235
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":11.123,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
CONSTRAINT 0.000 8.888 1
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 8.888 331
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141
NET DELAY 2.235 11.123 331
{CNT03/Couti_reg[13].ff_inst/CLK CNT03/Couti_reg[14].ff_inst/CLK}
CLOCK PIN 0.000 11.123 1
Uncertainty -(0.000) 11.123
Common Path Skew 0.028 11.151
Setup time -(0.197) 10.954
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
Required Time 10.954
Arrival Time -(7.426)
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
Path Slack (Passed) 3.527
++++ Path 10 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : rsti_0io.PIC_inst/Q (SIOLOGIC_CORE_IOL_R24A)
Path End : CNT03/Couti_reg[15].ff_inst/LSR (SLICE_R60C11A)
Source Clock : clk150 (R)
Destination Clock: clk150 (R)
Logic Level : 1
Delay Ratio : 91.6% (route), 8.4% (logic)
Clock Skew : -0.216 ns
Setup Constraint : 8.888 ns
Common Path Skew : 0.028 ns
Path Slack : 3.527 ns (Passed)
Source Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"rsti_0io.PIC_inst/CLK",
"phy_name":"reset_pad.bb_inst_IOL/SCLKIN"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":2.451,
"delay":2.451
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":2.451,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 331
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141
NET DELAY 2.451 2.451 331
rsti_0io.PIC_inst/CLK CLOCK PIN 0.000 2.451 1
Data Path
{
"path_begin":
{
"type":"pin",
"log_name":"rsti_0io.PIC_inst/Q",
"phy_name":"reset_pad.bb_inst_IOL/INFF"
},
"path_end":
{
"type":"pin",
"log_name":"CNT03/Couti_reg[15].ff_inst/LSR",
"phy_name":"CNT03.SLICE_128/LSR"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"rsti_0io.PIC_inst/CLK",
"phy_name":"reset_pad.bb_inst_IOL/SCLKIN"
},
"pin1":
{
"log_name":"rsti_0io.PIC_inst/Q",
"phy_name":"reset_pad.bb_inst_IOL/INFF"
},
"arrive":2.867,
"delay":0.416
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_signal_1_89",
"phy_name":"rsti_1"
},
"arrive":7.427,
"delay":4.560
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":7.427,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
rsti_0io.PIC_inst/CLK->rsti_0io.PIC_inst/Q
SIOLOGIC_CORE_IOL_R24A C2INP_DEL 0.416 2.867 38
top_reveal_coretop_instance/core0/tm_u/secured_signal_1_89
NET DELAY 4.560 7.427 38
CNT03/Couti_reg[15].ff_inst/LSR ENDPOINT 0.000 7.427 1
Destination Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"CNT03/Couti_reg[15].ff_inst/CLK",
"phy_name":"CNT03.SLICE_128/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":8.888,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":11.123,
"delay":2.235
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":11.123,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
CONSTRAINT 0.000 8.888 1
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 8.888 331
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141
NET DELAY 2.235 11.123 331
CNT03/Couti_reg[15].ff_inst/CLK CLOCK PIN 0.000 11.123 1
Uncertainty -(0.000) 11.123
Common Path Skew 0.028 11.151
Setup time -(0.197) 10.954
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
Required Time 10.954
Arrival Time -(7.426)
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
Path Slack (Passed) 3.527
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
End of Detailed Report for timing paths
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
##########################################################
3 Setup at Speed Grade 9_High-Performance_1.0V Corner at 0 Degrees
3.1 Clock Summary
3.1.1 Clock "clk150"
create_clock -name {clk150} -period 8.88889 [get_pins {OSCA001.OSCA_inst/HFCLKOUT }]
Single Clock Domain
-------------------------------------------------------------------------------------------------------
Clock clk150 | | Period | Frequency
-------------------------------------------------------------------------------------------------------
From clk150 | Target | 8.889 ns | 112.500 MHz
| Actual (all paths) | 5.793 ns | 172.622 MHz
OSCA001.OSCA_inst/HFCLKOUT (MPW) | (50% duty cycle) | 4.354 ns | 229.674 MHz
-------------------------------------------------------------------------------------------------------
Clock Domain Crossing
------------------------------------------------------------------------------------------------------
Clock clk150 | Worst Time Between Edges | Comment
------------------------------------------------------------------------------------------------------
From rvltck | ---- | False path
------------------------------------------------------------------------------------------------------
3.1.2 Clock "rvltck"
create_clock -name {rvltck} -period 33.33 [get_ports TCK]
Single Clock Domain
-------------------------------------------------------------------------------------------------------
Clock rvltck | | Period | Frequency
-------------------------------------------------------------------------------------------------------
From rvltck | Target | 33.330 ns | 30.003 MHz
| Actual (all paths) | 5.000 ns | 200.000 MHz
jtaghub_inst/IB_inst2.bb_inst/B (MPW) | (50% duty cycle) | 5.000 ns | 200.000 MHz
-------------------------------------------------------------------------------------------------------
Clock Domain Crossing
------------------------------------------------------------------------------------------------------
Clock rvltck | Worst Time Between Edges | Comment
------------------------------------------------------------------------------------------------------
From clk150 | ---- | False path
------------------------------------------------------------------------------------------------------
3.2 Endpoint slacks
-------------------------------------------------------
Listing 10 End Points | Slack
-------------------------------------------------------
LED3_0io.PIC_inst/D | 3.096 ns
LED1_0io.PIC_inst/D | 3.188 ns
{top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_103/CE top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_104/CE}
| 3.354 ns
CNT03/Couti_reg[0].ff_inst/LSR | 3.354 ns
{CNT03/Couti_reg[1].ff_inst/LSR CNT03/Couti_reg[2].ff_inst/LSR}
| 3.354 ns
{CNT03/Couti_reg[3].ff_inst/LSR CNT03/Couti_reg[4].ff_inst/LSR}
| 3.354 ns
{CNT03/Couti_reg[5].ff_inst/LSR CNT03/Couti_reg[6].ff_inst/LSR}
| 3.354 ns
{CNT03/Couti_reg[11].ff_inst/LSR CNT03/Couti_reg[12].ff_inst/LSR}
| 3.470 ns
{CNT03/Couti_reg[13].ff_inst/LSR CNT03/Couti_reg[14].ff_inst/LSR}
| 3.470 ns
CNT03/Couti_reg[15].ff_inst/LSR | 3.470 ns
-------------------------------------------------------
|
Setup # of endpoints with negative slack:| 0
|
-------------------------------------------------------
3.3 Detailed Report
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
Detail report of critical paths
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Detailed Report for timing paths
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++++Path 1 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : CNT03/Couti_reg[15].ff_inst/Q (SLICE_R60C11A)
Path End : LED3_0io.PIC_inst/D (SIOLOGIC_CORE_IOL_R31A)
Source Clock : clk150 (R)
Destination Clock: clk150 (R)
Logic Level : 2
Delay Ratio : 90.8% (route), 9.2% (logic)
Clock Skew : -0.096 ns
Setup Constraint : 8.888 ns
Common Path Skew : 0.030 ns
Path Slack : 3.095 ns (Passed)
Source Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"CNT03/Couti_reg[15].ff_inst/CLK",
"phy_name":"CNT03.SLICE_128/CLK"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":2.544,
"delay":2.544
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":2.544,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 332
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141
NET DELAY 2.544 2.544 332
CNT03/Couti_reg[15].ff_inst/CLK CLOCK PIN 0.000 2.544 1
Data Path
{
"path_begin":
{
"type":"pin",
"log_name":"CNT03/Couti_reg[15].ff_inst/Q",
"phy_name":"CNT03.SLICE_128/Q0"
},
"path_end":
{
"type":"pin",
"log_name":"LED3_0io.PIC_inst/D",
"phy_name":"LED3_pad.bb_inst_IOL/TXDATA0"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"CNT03/Couti_reg[15].ff_inst/CLK",
"phy_name":"CNT03.SLICE_128/CLK"
},
"pin1":
{
"log_name":"CNT03/Couti_reg[15].ff_inst/Q",
"phy_name":"CNT03.SLICE_128/Q0"
},
"arrive":2.837,
"delay":0.293
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_signal_1_57",
"phy_name":"CNT3[15]"
},
"arrive":5.371,
"delay":2.534
},
{
"type":"site_delay",
"pin0":
{
"log_name":"LED3_1_cZ/B",
"phy_name":"SLICE_1030/B1"
},
"pin1":
{
"log_name":"LED3_1_cZ/Z",
"phy_name":"SLICE_1030/F1"
},
"arrive":5.576,
"delay":0.205
},
{
"type":"net_delay",
"net":
{
"log_name":"LED3_1",
"phy_name":"LED3_1"
},
"arrive":7.952,
"delay":2.376
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":7.952,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
CNT03/Couti_reg[15].ff_inst/CLK->CNT03/Couti_reg[15].ff_inst/Q
SLICE_R60C11A REG_DEL 0.293 2.837 4
top_reveal_coretop_instance/core0/tm_u/secured_signal_1_57
NET DELAY 2.534 5.371 4
LED3_1_cZ/B->LED3_1_cZ/Z SLICE_R35C78B CTOF_DEL 0.205 5.576 1
LED3_1 NET DELAY 2.376 7.952 1
LED3_0io.PIC_inst/D ENDPOINT 0.000 7.952 1
Destination Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"LED3_0io.PIC_inst/CLK",
"phy_name":"LED3_pad.bb_inst_IOL/SCLKOUT"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":8.888,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":11.336,
"delay":2.448
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":11.336,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
CONSTRAINT 0.000 8.888 1
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 8.888 332
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141
NET DELAY 2.448 11.336 332
LED3_0io.PIC_inst/CLK CLOCK PIN 0.000 11.336 1
Uncertainty -(0.000) 11.336
Common Path Skew 0.030 11.366
Setup time -(0.319) 11.047
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
Required Time 11.047
Arrival Time -(7.951)
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
Path Slack (Passed) 3.095
++++ Path 2 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : CNT01/Couti_reg[15].ff_inst/Q (SLICE_R14C14A)
Path End : LED1_0io.PIC_inst/D (SIOLOGIC_CORE_IOL_R28B)
Source Clock : clk150 (R)
Destination Clock: clk150 (R)
Logic Level : 2
Delay Ratio : 90.6% (route), 9.4% (logic)
Clock Skew : -0.096 ns
Setup Constraint : 8.888 ns
Common Path Skew : 0.030 ns
Path Slack : 3.187 ns (Passed)
Source Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"CNT01/Couti_reg[15].ff_inst/CLK",
"phy_name":"CNT01.SLICE_110/CLK"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":2.544,
"delay":2.544
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":2.544,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 332
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141
NET DELAY 2.544 2.544 332
CNT01/Couti_reg[15].ff_inst/CLK CLOCK PIN 0.000 2.544 1
Data Path
{
"path_begin":
{
"type":"pin",
"log_name":"CNT01/Couti_reg[15].ff_inst/Q",
"phy_name":"CNT01.SLICE_110/Q0"
},
"path_end":
{
"type":"pin",
"log_name":"LED1_0io.PIC_inst/D",
"phy_name":"LED1_pad.bb_inst_IOL/TXDATA0"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"CNT01/Couti_reg[15].ff_inst/CLK",
"phy_name":"CNT01.SLICE_110/CLK"
},
"pin1":
{
"log_name":"CNT01/Couti_reg[15].ff_inst/Q",
"phy_name":"CNT01.SLICE_110/Q0"
},
"arrive":2.837,
"delay":0.293
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_signal_1_25",
"phy_name":"CNT1[15]"
},
"arrive":5.187,
"delay":2.350
},
{
"type":"site_delay",
"pin0":
{
"log_name":"LED1_1_cZ/B",
"phy_name":"SLICE_1028/B1"
},
"pin1":
{
"log_name":"LED1_1_cZ/Z",
"phy_name":"SLICE_1028/F1"
},
"arrive":5.392,
"delay":0.205
},
{
"type":"net_delay",
"net":
{
"log_name":"LED1_1",
"phy_name":"LED1_1"
},
"arrive":7.860,
"delay":2.468
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":7.860,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
CNT01/Couti_reg[15].ff_inst/CLK->CNT01/Couti_reg[15].ff_inst/Q
SLICE_R14C14A REG_DEL 0.293 2.837 4
top_reveal_coretop_instance/core0/tm_u/secured_signal_1_25
NET DELAY 2.350 5.187 4
LED1_1_cZ/B->LED1_1_cZ/Z SLICE_R33C79D CTOF_DEL 0.205 5.392 1
LED1_1 NET DELAY 2.468 7.860 1
LED1_0io.PIC_inst/D ENDPOINT 0.000 7.860 1
Destination Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"LED1_0io.PIC_inst/CLK",
"phy_name":"LED1_pad.bb_inst_IOL/SCLKOUT"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":8.888,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":11.336,
"delay":2.448
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":11.336,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
CONSTRAINT 0.000 8.888 1
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 8.888 332
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141
NET DELAY 2.448 11.336 332
LED1_0io.PIC_inst/CLK CLOCK PIN 0.000 11.336 1
Uncertainty -(0.000) 11.336
Common Path Skew 0.030 11.366
Setup time -(0.319) 11.047
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
Required Time 11.047
Arrival Time -(7.859)
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
Path Slack (Passed) 3.187
++++ Path 3 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_468/Q (SLICE_R36C82B)
Path End : {top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_103/CE top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_104/CE} (SLICE_R43C72B)
Source Clock : clk150 (R)
Destination Clock: clk150 (R)
Logic Level : 7
Delay Ratio : 70.3% (route), 29.7% (logic)
Clock Skew : -0.142 ns
Setup Constraint : 8.888 ns
Common Path Skew : 0.030 ns
Path Slack : 3.353 ns (Passed)
Source Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_467/CLK",
"phy_name":"top_reveal_coretop_instance.core0.jtag_int_u.SLICE_1248/CLK"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":2.544,
"delay":2.544
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":2.544,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 332
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141
NET DELAY 2.544 2.544 332
{top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_467/CLK top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_468/CLK}
CLOCK PIN 0.000 2.544 1
Data Path
{
"path_begin":
{
"type":"pin",
"log_name":"top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_468/Q",
"phy_name":"top_reveal_coretop_instance.core0.jtag_int_u.SLICE_1248/Q1"
},
"path_end":
{
"type":"pin",
"log_name":"{top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_103/CE top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_104/CE}",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tu_3.IhL6rK7kjDdr78xjJ[4].SLICE_824/CE"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_468/CLK",
"phy_name":"top_reveal_coretop_instance.core0.jtag_int_u.SLICE_1248/CLK"
},
"pin1":
{
"log_name":"top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_468/Q",
"phy_name":"top_reveal_coretop_instance.core0.jtag_int_u.SLICE_1248/Q1"
},
"arrive":2.852,
"delay":0.308
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/jtag_int_u/secured_signal_2_155",
"phy_name":"top_reveal_coretop_instance.core0.jtag_int_u.Ne3nFILyd5q303pD9C8l[3]"
},
"arrive":3.245,
"delay":0.393
},
{
"type":"site_delay",
"pin0":
{
"log_name":"top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_243/B",
"phy_name":"top_reveal_coretop_instance.core0.jtag_int_u.SLICE_1248/C0"
},
"pin1":
{
"log_name":"top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_243/Z",
"phy_name":"top_reveal_coretop_instance.core0.jtag_int_u.SLICE_1248/F0"
},
"arrive":3.450,
"delay":0.205
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/jtag_int_u/secured_signal_2_577",
"phy_name":"top_reveal_coretop_instance.core0.jtag_int_u.Nb4zmjgl42aqur7c"
},
"arrive":3.886,
"delay":0.436
},
{
"type":"site_delay",
"pin0":
{
"log_name":"top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_233/D",
"phy_name":"top_reveal_coretop_instance.core0.jtag_int_u.SLICE_1241/B1"
},
"pin1":
{
"log_name":"top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_233/Z",
"phy_name":"top_reveal_coretop_instance.core0.jtag_int_u.SLICE_1241/F1"
},
"arrive":4.091,
"delay":0.205
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_signal_1_157",
"phy_name":"top_reveal_coretop_instance.core0.wen"
},
"arrive":4.656,
"delay":0.565
},
{
"type":"site_delay",
"pin0":
{
"log_name":"top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_15_17/B",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.decode_u.SLICE_1756/C1"
},
"pin1":
{
"log_name":"top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_15_17/Z",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.decode_u.SLICE_1756/F1"
},
"arrive":4.869,
"delay":0.213
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/trig_u/decode_u/secured_signal_15_26",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.decode_u.Nfh7o1A"
},
"arrive":5.149,
"delay":0.280
},
{
"type":"site_delay",
"pin0":
{
"log_name":"top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_15_6/A",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.decode_u.SLICE_1748/A1"
},
"pin1":
{
"log_name":"top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_15_6/Z",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.decode_u.SLICE_1748/F1"
},
"arrive":5.354,
"delay":0.205
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/trig_u/decode_u/secured_signal_15_28",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.decode_u.Nfh7o1E"
},
"arrive":5.995,
"delay":0.641
},
{
"type":"site_delay",
"pin0":
{
"log_name":"top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_15_3/A",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tu_3.SLICE_1518/B1"
},
"pin1":
{
"log_name":"top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_15_3/Z",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tu_3.SLICE_1518/F1"
},
"arrive":6.208,
"delay":0.213
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/trig_u/tu_3/secured_signal_11_56",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.wen_tu[3]"
},
"arrive":6.478,
"delay":0.270
},
{
"type":"site_delay",
"pin0":
{
"log_name":"top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_5/C",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tu_3.SLICE_1517/A0"
},
"pin1":
{
"log_name":"top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_5/Z",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tu_3.SLICE_1517/F0"
},
"arrive":6.683,
"delay":0.205
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/trig_u/tu_3/secured_signal_11_149",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tu_3.NfmqpHfyLjihmE893lg93s3sdHIgm7"
},
"arrive":7.783,
"delay":1.100
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":7.783,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_468/CLK->top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_468/Q
SLICE_R36C82B REG_DEL 0.308 2.852 4
top_reveal_coretop_instance/core0/jtag_int_u/secured_signal_2_155
NET DELAY 0.393 3.245 4
top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_243/B->top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_243/Z
SLICE_R36C82B CTOF_DEL 0.205 3.450 1
top_reveal_coretop_instance/core0/jtag_int_u/secured_signal_2_577
NET DELAY 0.436 3.886 1
top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_233/D->top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_233/Z
SLICE_R38C81B CTOF_DEL 0.205 4.091 5
top_reveal_coretop_instance/core0/tm_u/secured_signal_1_157
NET DELAY 0.565 4.656 5
top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_15_17/B->top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_15_17/Z
SLICE_R32C78B CTOF_DEL 0.213 4.869 3
top_reveal_coretop_instance/core0/trig_u/decode_u/secured_signal_15_26
NET DELAY 0.280 5.149 3
top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_15_6/A->top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_15_6/Z
SLICE_R33C78A CTOF_DEL 0.205 5.354 3
top_reveal_coretop_instance/core0/trig_u/decode_u/secured_signal_15_28
NET DELAY 0.641 5.995 3
top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_15_3/A->top_reveal_coretop_instance/core0/trig_u/decode_u/secured_instance_15_3/Z
SLICE_R36C82C CTOF_DEL 0.213 6.208 3
top_reveal_coretop_instance/core0/trig_u/tu_3/secured_signal_11_56
NET DELAY 0.270 6.478 3
top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_5/C->top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_5/Z
SLICE_R36C83C CTOF_DEL 0.205 6.683 8
top_reveal_coretop_instance/core0/trig_u/tu_3/secured_signal_11_149
NET DELAY 1.100 7.783 8
{top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_103/CE top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_104/CE}
ENDPOINT 0.000 7.783 1
Destination Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_103/CLK",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tu_3.IhL6rK7kjDdr78xjJ[4].SLICE_824/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":8.888,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":11.290,
"delay":2.402
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":11.290,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
CONSTRAINT 0.000 8.888 1
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 8.888 332
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141
NET DELAY 2.402 11.290 332
{top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_103/CLK top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_104/CLK}
CLOCK PIN 0.000 11.290 1
Uncertainty -(0.000) 11.290
Common Path Skew 0.030 11.320
Setup time -(0.184) 11.136
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
Required Time 11.136
Arrival Time -(7.782)
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
Path Slack (Passed) 3.353
++++ Path 4 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : rsti_0io.PIC_inst/Q (SIOLOGIC_CORE_IOL_R24A)
Path End : CNT03/Couti_reg[0].ff_inst/LSR (SLICE_R60C9A)
Source Clock : clk150 (R)
Destination Clock: clk150 (R)
Logic Level : 1
Delay Ratio : 91.2% (route), 8.8% (logic)
Clock Skew : -0.226 ns
Setup Constraint : 8.888 ns
Common Path Skew : 0.030 ns
Path Slack : 3.353 ns (Passed)
Source Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"rsti_0io.PIC_inst/CLK",
"phy_name":"reset_pad.bb_inst_IOL/SCLKIN"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":2.628,
"delay":2.628
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":2.628,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 332
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141
NET DELAY 2.628 2.628 332
rsti_0io.PIC_inst/CLK CLOCK PIN 0.000 2.628 1
Data Path
{
"path_begin":
{
"type":"pin",
"log_name":"rsti_0io.PIC_inst/Q",
"phy_name":"reset_pad.bb_inst_IOL/INFF"
},
"path_end":
{
"type":"pin",
"log_name":"CNT03/Couti_reg[0].ff_inst/LSR",
"phy_name":"CNT03.SLICE_136/LSR"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"rsti_0io.PIC_inst/CLK",
"phy_name":"reset_pad.bb_inst_IOL/SCLKIN"
},
"pin1":
{
"log_name":"rsti_0io.PIC_inst/Q",
"phy_name":"reset_pad.bb_inst_IOL/INFF"
},
"arrive":3.080,
"delay":0.452
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_signal_1_89",
"phy_name":"rsti_1"
},
"arrive":7.770,
"delay":4.690
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":7.770,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
rsti_0io.PIC_inst/CLK->rsti_0io.PIC_inst/Q
SIOLOGIC_CORE_IOL_R24A C2INP_DEL 0.452 3.080 38
top_reveal_coretop_instance/core0/tm_u/secured_signal_1_89
NET DELAY 4.690 7.770 38
CNT03/Couti_reg[0].ff_inst/LSR ENDPOINT 0.000 7.770 1
Destination Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"CNT03/Couti_reg[0].ff_inst/CLK",
"phy_name":"CNT03.SLICE_136/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":8.888,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":11.290,
"delay":2.402
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":11.290,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
CONSTRAINT 0.000 8.888 1
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 8.888 332
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141
NET DELAY 2.402 11.290 332
CNT03/Couti_reg[0].ff_inst/CLK CLOCK PIN 0.000 11.290 1
Uncertainty -(0.000) 11.290
Common Path Skew 0.030 11.320
Setup time -(0.197) 11.123
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
Required Time 11.123
Arrival Time -(7.769)
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
Path Slack (Passed) 3.353
++++ Path 5 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : rsti_0io.PIC_inst/Q (SIOLOGIC_CORE_IOL_R24A)
Path End : {CNT03/Couti_reg[1].ff_inst/LSR CNT03/Couti_reg[2].ff_inst/LSR} (SLICE_R60C9B)
Source Clock : clk150 (R)
Destination Clock: clk150 (R)
Logic Level : 1
Delay Ratio : 91.2% (route), 8.8% (logic)
Clock Skew : -0.226 ns
Setup Constraint : 8.888 ns
Common Path Skew : 0.030 ns
Path Slack : 3.353 ns (Passed)
Source Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"rsti_0io.PIC_inst/CLK",
"phy_name":"reset_pad.bb_inst_IOL/SCLKIN"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":2.628,
"delay":2.628
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":2.628,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 332
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141
NET DELAY 2.628 2.628 332
rsti_0io.PIC_inst/CLK CLOCK PIN 0.000 2.628 1
Data Path
{
"path_begin":
{
"type":"pin",
"log_name":"rsti_0io.PIC_inst/Q",
"phy_name":"reset_pad.bb_inst_IOL/INFF"
},
"path_end":
{
"type":"pin",
"log_name":"{CNT03/Couti_reg[1].ff_inst/LSR CNT03/Couti_reg[2].ff_inst/LSR}",
"phy_name":"CNT03.SLICE_135/LSR"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"rsti_0io.PIC_inst/CLK",
"phy_name":"reset_pad.bb_inst_IOL/SCLKIN"
},
"pin1":
{
"log_name":"rsti_0io.PIC_inst/Q",
"phy_name":"reset_pad.bb_inst_IOL/INFF"
},
"arrive":3.080,
"delay":0.452
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_signal_1_89",
"phy_name":"rsti_1"
},
"arrive":7.770,
"delay":4.690
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":7.770,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
rsti_0io.PIC_inst/CLK->rsti_0io.PIC_inst/Q
SIOLOGIC_CORE_IOL_R24A C2INP_DEL 0.452 3.080 38
top_reveal_coretop_instance/core0/tm_u/secured_signal_1_89
NET DELAY 4.690 7.770 38
{CNT03/Couti_reg[1].ff_inst/LSR CNT03/Couti_reg[2].ff_inst/LSR}
ENDPOINT 0.000 7.770 1
Destination Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"CNT03/Couti_reg[1].ff_inst/CLK",
"phy_name":"CNT03.SLICE_135/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":8.888,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":11.290,
"delay":2.402
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":11.290,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
CONSTRAINT 0.000 8.888 1
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 8.888 332
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141
NET DELAY 2.402 11.290 332
{CNT03/Couti_reg[1].ff_inst/CLK CNT03/Couti_reg[2].ff_inst/CLK}
CLOCK PIN 0.000 11.290 1
Uncertainty -(0.000) 11.290
Common Path Skew 0.030 11.320
Setup time -(0.197) 11.123
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
Required Time 11.123
Arrival Time -(7.769)
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
Path Slack (Passed) 3.353
++++ Path 6 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : rsti_0io.PIC_inst/Q (SIOLOGIC_CORE_IOL_R24A)
Path End : {CNT03/Couti_reg[3].ff_inst/LSR CNT03/Couti_reg[4].ff_inst/LSR} (SLICE_R60C9C)
Source Clock : clk150 (R)
Destination Clock: clk150 (R)
Logic Level : 1
Delay Ratio : 91.2% (route), 8.8% (logic)
Clock Skew : -0.226 ns
Setup Constraint : 8.888 ns
Common Path Skew : 0.030 ns
Path Slack : 3.353 ns (Passed)
Source Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"rsti_0io.PIC_inst/CLK",
"phy_name":"reset_pad.bb_inst_IOL/SCLKIN"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":2.628,
"delay":2.628
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":2.628,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 332
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141
NET DELAY 2.628 2.628 332
rsti_0io.PIC_inst/CLK CLOCK PIN 0.000 2.628 1
Data Path
{
"path_begin":
{
"type":"pin",
"log_name":"rsti_0io.PIC_inst/Q",
"phy_name":"reset_pad.bb_inst_IOL/INFF"
},
"path_end":
{
"type":"pin",
"log_name":"{CNT03/Couti_reg[3].ff_inst/LSR CNT03/Couti_reg[4].ff_inst/LSR}",
"phy_name":"CNT03.SLICE_134/LSR"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"rsti_0io.PIC_inst/CLK",
"phy_name":"reset_pad.bb_inst_IOL/SCLKIN"
},
"pin1":
{
"log_name":"rsti_0io.PIC_inst/Q",
"phy_name":"reset_pad.bb_inst_IOL/INFF"
},
"arrive":3.080,
"delay":0.452
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_signal_1_89",
"phy_name":"rsti_1"
},
"arrive":7.770,
"delay":4.690
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":7.770,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
rsti_0io.PIC_inst/CLK->rsti_0io.PIC_inst/Q
SIOLOGIC_CORE_IOL_R24A C2INP_DEL 0.452 3.080 38
top_reveal_coretop_instance/core0/tm_u/secured_signal_1_89
NET DELAY 4.690 7.770 38
{CNT03/Couti_reg[3].ff_inst/LSR CNT03/Couti_reg[4].ff_inst/LSR}
ENDPOINT 0.000 7.770 1
Destination Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"CNT03/Couti_reg[3].ff_inst/CLK",
"phy_name":"CNT03.SLICE_134/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":8.888,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":11.290,
"delay":2.402
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":11.290,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
CONSTRAINT 0.000 8.888 1
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 8.888 332
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141
NET DELAY 2.402 11.290 332
{CNT03/Couti_reg[3].ff_inst/CLK CNT03/Couti_reg[4].ff_inst/CLK}
CLOCK PIN 0.000 11.290 1
Uncertainty -(0.000) 11.290
Common Path Skew 0.030 11.320
Setup time -(0.197) 11.123
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
Required Time 11.123
Arrival Time -(7.769)
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
Path Slack (Passed) 3.353
++++ Path 7 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : rsti_0io.PIC_inst/Q (SIOLOGIC_CORE_IOL_R24A)
Path End : {CNT03/Couti_reg[5].ff_inst/LSR CNT03/Couti_reg[6].ff_inst/LSR} (SLICE_R60C9D)
Source Clock : clk150 (R)
Destination Clock: clk150 (R)
Logic Level : 1
Delay Ratio : 91.2% (route), 8.8% (logic)
Clock Skew : -0.226 ns
Setup Constraint : 8.888 ns
Common Path Skew : 0.030 ns
Path Slack : 3.353 ns (Passed)
Source Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"rsti_0io.PIC_inst/CLK",
"phy_name":"reset_pad.bb_inst_IOL/SCLKIN"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":2.628,
"delay":2.628
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":2.628,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 332
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141
NET DELAY 2.628 2.628 332
rsti_0io.PIC_inst/CLK CLOCK PIN 0.000 2.628 1
Data Path
{
"path_begin":
{
"type":"pin",
"log_name":"rsti_0io.PIC_inst/Q",
"phy_name":"reset_pad.bb_inst_IOL/INFF"
},
"path_end":
{
"type":"pin",
"log_name":"{CNT03/Couti_reg[5].ff_inst/LSR CNT03/Couti_reg[6].ff_inst/LSR}",
"phy_name":"CNT03.SLICE_133/LSR"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"rsti_0io.PIC_inst/CLK",
"phy_name":"reset_pad.bb_inst_IOL/SCLKIN"
},
"pin1":
{
"log_name":"rsti_0io.PIC_inst/Q",
"phy_name":"reset_pad.bb_inst_IOL/INFF"
},
"arrive":3.080,
"delay":0.452
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_signal_1_89",
"phy_name":"rsti_1"
},
"arrive":7.770,
"delay":4.690
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":7.770,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
rsti_0io.PIC_inst/CLK->rsti_0io.PIC_inst/Q
SIOLOGIC_CORE_IOL_R24A C2INP_DEL 0.452 3.080 38
top_reveal_coretop_instance/core0/tm_u/secured_signal_1_89
NET DELAY 4.690 7.770 38
{CNT03/Couti_reg[5].ff_inst/LSR CNT03/Couti_reg[6].ff_inst/LSR}
ENDPOINT 0.000 7.770 1
Destination Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"CNT03/Couti_reg[5].ff_inst/CLK",
"phy_name":"CNT03.SLICE_133/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":8.888,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":11.290,
"delay":2.402
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":11.290,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
CONSTRAINT 0.000 8.888 1
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 8.888 332
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141
NET DELAY 2.402 11.290 332
{CNT03/Couti_reg[5].ff_inst/CLK CNT03/Couti_reg[6].ff_inst/CLK}
CLOCK PIN 0.000 11.290 1
Uncertainty -(0.000) 11.290
Common Path Skew 0.030 11.320
Setup time -(0.197) 11.123
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
Required Time 11.123
Arrival Time -(7.769)
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
Path Slack (Passed) 3.353
++++ Path 8 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : rsti_0io.PIC_inst/Q (SIOLOGIC_CORE_IOL_R24A)
Path End : {CNT03/Couti_reg[11].ff_inst/LSR CNT03/Couti_reg[12].ff_inst/LSR} (SLICE_R60C10C)
Source Clock : clk150 (R)
Destination Clock: clk150 (R)
Logic Level : 1
Delay Ratio : 91.0% (route), 9.0% (logic)
Clock Skew : -0.226 ns
Setup Constraint : 8.888 ns
Common Path Skew : 0.030 ns
Path Slack : 3.469 ns (Passed)
Source Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"rsti_0io.PIC_inst/CLK",
"phy_name":"reset_pad.bb_inst_IOL/SCLKIN"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":2.628,
"delay":2.628
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":2.628,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 332
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141
NET DELAY 2.628 2.628 332
rsti_0io.PIC_inst/CLK CLOCK PIN 0.000 2.628 1
Data Path
{
"path_begin":
{
"type":"pin",
"log_name":"rsti_0io.PIC_inst/Q",
"phy_name":"reset_pad.bb_inst_IOL/INFF"
},
"path_end":
{
"type":"pin",
"log_name":"{CNT03/Couti_reg[11].ff_inst/LSR CNT03/Couti_reg[12].ff_inst/LSR}",
"phy_name":"CNT03.SLICE_130/LSR"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"rsti_0io.PIC_inst/CLK",
"phy_name":"reset_pad.bb_inst_IOL/SCLKIN"
},
"pin1":
{
"log_name":"rsti_0io.PIC_inst/Q",
"phy_name":"reset_pad.bb_inst_IOL/INFF"
},
"arrive":3.080,
"delay":0.452
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_signal_1_89",
"phy_name":"rsti_1"
},
"arrive":7.654,
"delay":4.574
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":7.654,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
rsti_0io.PIC_inst/CLK->rsti_0io.PIC_inst/Q
SIOLOGIC_CORE_IOL_R24A C2INP_DEL 0.452 3.080 38
top_reveal_coretop_instance/core0/tm_u/secured_signal_1_89
NET DELAY 4.574 7.654 38
{CNT03/Couti_reg[11].ff_inst/LSR CNT03/Couti_reg[12].ff_inst/LSR}
ENDPOINT 0.000 7.654 1
Destination Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"CNT03/Couti_reg[11].ff_inst/CLK",
"phy_name":"CNT03.SLICE_130/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":8.888,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":11.290,
"delay":2.402
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":11.290,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
CONSTRAINT 0.000 8.888 1
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 8.888 332
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141
NET DELAY 2.402 11.290 332
{CNT03/Couti_reg[11].ff_inst/CLK CNT03/Couti_reg[12].ff_inst/CLK}
CLOCK PIN 0.000 11.290 1
Uncertainty -(0.000) 11.290
Common Path Skew 0.030 11.320
Setup time -(0.197) 11.123
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
Required Time 11.123
Arrival Time -(7.653)
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
Path Slack (Passed) 3.469
++++ Path 9 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : rsti_0io.PIC_inst/Q (SIOLOGIC_CORE_IOL_R24A)
Path End : {CNT03/Couti_reg[13].ff_inst/LSR CNT03/Couti_reg[14].ff_inst/LSR} (SLICE_R60C10D)
Source Clock : clk150 (R)
Destination Clock: clk150 (R)
Logic Level : 1
Delay Ratio : 91.0% (route), 9.0% (logic)
Clock Skew : -0.226 ns
Setup Constraint : 8.888 ns
Common Path Skew : 0.030 ns
Path Slack : 3.469 ns (Passed)
Source Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"rsti_0io.PIC_inst/CLK",
"phy_name":"reset_pad.bb_inst_IOL/SCLKIN"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":2.628,
"delay":2.628
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":2.628,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 332
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141
NET DELAY 2.628 2.628 332
rsti_0io.PIC_inst/CLK CLOCK PIN 0.000 2.628 1
Data Path
{
"path_begin":
{
"type":"pin",
"log_name":"rsti_0io.PIC_inst/Q",
"phy_name":"reset_pad.bb_inst_IOL/INFF"
},
"path_end":
{
"type":"pin",
"log_name":"{CNT03/Couti_reg[13].ff_inst/LSR CNT03/Couti_reg[14].ff_inst/LSR}",
"phy_name":"CNT03.SLICE_129/LSR"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"rsti_0io.PIC_inst/CLK",
"phy_name":"reset_pad.bb_inst_IOL/SCLKIN"
},
"pin1":
{
"log_name":"rsti_0io.PIC_inst/Q",
"phy_name":"reset_pad.bb_inst_IOL/INFF"
},
"arrive":3.080,
"delay":0.452
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_signal_1_89",
"phy_name":"rsti_1"
},
"arrive":7.654,
"delay":4.574
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":7.654,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
rsti_0io.PIC_inst/CLK->rsti_0io.PIC_inst/Q
SIOLOGIC_CORE_IOL_R24A C2INP_DEL 0.452 3.080 38
top_reveal_coretop_instance/core0/tm_u/secured_signal_1_89
NET DELAY 4.574 7.654 38
{CNT03/Couti_reg[13].ff_inst/LSR CNT03/Couti_reg[14].ff_inst/LSR}
ENDPOINT 0.000 7.654 1
Destination Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"CNT03/Couti_reg[13].ff_inst/CLK",
"phy_name":"CNT03.SLICE_129/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":8.888,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":11.290,
"delay":2.402
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":11.290,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
CONSTRAINT 0.000 8.888 1
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 8.888 332
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141
NET DELAY 2.402 11.290 332
{CNT03/Couti_reg[13].ff_inst/CLK CNT03/Couti_reg[14].ff_inst/CLK}
CLOCK PIN 0.000 11.290 1
Uncertainty -(0.000) 11.290
Common Path Skew 0.030 11.320
Setup time -(0.197) 11.123
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
Required Time 11.123
Arrival Time -(7.653)
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
Path Slack (Passed) 3.469
++++ Path 10 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : rsti_0io.PIC_inst/Q (SIOLOGIC_CORE_IOL_R24A)
Path End : CNT03/Couti_reg[15].ff_inst/LSR (SLICE_R60C11A)
Source Clock : clk150 (R)
Destination Clock: clk150 (R)
Logic Level : 1
Delay Ratio : 91.0% (route), 9.0% (logic)
Clock Skew : -0.226 ns
Setup Constraint : 8.888 ns
Common Path Skew : 0.030 ns
Path Slack : 3.469 ns (Passed)
Source Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"rsti_0io.PIC_inst/CLK",
"phy_name":"reset_pad.bb_inst_IOL/SCLKIN"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":2.628,
"delay":2.628
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":2.628,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 332
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141
NET DELAY 2.628 2.628 332
rsti_0io.PIC_inst/CLK CLOCK PIN 0.000 2.628 1
Data Path
{
"path_begin":
{
"type":"pin",
"log_name":"rsti_0io.PIC_inst/Q",
"phy_name":"reset_pad.bb_inst_IOL/INFF"
},
"path_end":
{
"type":"pin",
"log_name":"CNT03/Couti_reg[15].ff_inst/LSR",
"phy_name":"CNT03.SLICE_128/LSR"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"rsti_0io.PIC_inst/CLK",
"phy_name":"reset_pad.bb_inst_IOL/SCLKIN"
},
"pin1":
{
"log_name":"rsti_0io.PIC_inst/Q",
"phy_name":"reset_pad.bb_inst_IOL/INFF"
},
"arrive":3.080,
"delay":0.452
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_signal_1_89",
"phy_name":"rsti_1"
},
"arrive":7.654,
"delay":4.574
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":7.654,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
rsti_0io.PIC_inst/CLK->rsti_0io.PIC_inst/Q
SIOLOGIC_CORE_IOL_R24A C2INP_DEL 0.452 3.080 38
top_reveal_coretop_instance/core0/tm_u/secured_signal_1_89
NET DELAY 4.574 7.654 38
CNT03/Couti_reg[15].ff_inst/LSR ENDPOINT 0.000 7.654 1
Destination Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"CNT03/Couti_reg[15].ff_inst/CLK",
"phy_name":"CNT03.SLICE_128/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":8.888,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":11.290,
"delay":2.402
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":11.290,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
CONSTRAINT 0.000 8.888 1
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 8.888 332
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141
NET DELAY 2.402 11.290 332
CNT03/Couti_reg[15].ff_inst/CLK CLOCK PIN 0.000 11.290 1
Uncertainty -(0.000) 11.290
Common Path Skew 0.030 11.320
Setup time -(0.197) 11.123
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
Required Time 11.123
Arrival Time -(7.653)
---------------------------------------- ------------------------ ---------------- -------- --------------------- ------
Path Slack (Passed) 3.469
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
End of Detailed Report for timing paths
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
##########################################################
4 Hold at Speed Grade m Corner at 0 Degrees
4.1 Endpoint slacks
-------------------------------------------------------
Listing 10 End Points | Slack
-------------------------------------------------------
top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_121/DF
| 0.109 ns
top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_120/DF
| 0.161 ns
top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_116/DF
| 0.167 ns
top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_122/DF
| 0.169 ns
top_reveal_coretop_instance/core0/trig_u/tu_4/secured_instance_10_115/DF
| 0.169 ns
top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_482/DF
| 0.169 ns
top_reveal_coretop_instance/core0/trig_u/tu_2/secured_instance_12_130/DF
| 0.170 ns
top_reveal_coretop_instance/core0/trig_u/tu_2/secured_instance_12_128/DF
| 0.170 ns
top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_130/DF
| 0.170 ns
top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_484/DF
| 0.170 ns
-------------------------------------------------------
|
Hold # of endpoints with negative slack: | 0
|
-------------------------------------------------------
4.2 Detailed Report
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
Detail report of critical paths
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Detailed Report for timing paths
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++++Path 1 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_137/Q (SLICE_R33C74A)
Path End : top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_121/DF (SLICE_R33C73D)
Source Clock : clk150 (R)
Destination Clock: clk150 (R)
Logic Level : 1
Delay Ratio : 37.3% (route), 62.7% (logic)
Clock Skew : 0.111 ns
Hold Constraint : 0.000 ns
Common Path Skew : -0.041 ns
Path Slack : 0.109 ns (Passed)
Source Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_137/CLK",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tu_1.SLICE_1662/CLK"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":1.767,
"delay":1.767
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":1.767,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- ------ --------------------- ------
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 333
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141
NET DELAY 1.767 1.767 333
top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_137/CLK
CLOCK PIN 0.000 1.767 1
Data Path
{
"path_begin":
{
"type":"pin",
"log_name":"top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_137/Q",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tu_1.SLICE_1662/Q0"
},
"path_end":
{
"type":"pin",
"log_name":"top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_121/DF",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tu_1.SLICE_1670/M0"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_137/CLK",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tu_1.SLICE_1662/CLK"
},
"pin1":
{
"log_name":"top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_137/Q",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tu_1.SLICE_1662/Q0"
},
"arrive":1.940,
"delay":0.173
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/trig_u/tu_1/secured_signal_13_137",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tu_1.Nc8pHcEsIxIrg"
},
"arrive":2.043,
"delay":0.103
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":2.043,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- ------ --------------------- ------
top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_137/CLK->top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_137/Q
SLICE_R33C74A REG_DEL 0.173 1.940 5
top_reveal_coretop_instance/core0/trig_u/tu_1/secured_signal_13_137
NET DELAY 0.103 2.043 5
top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_121/DF
ENDPOINT 0.000 2.043 1
Destination Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_121/CLK",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tu_1.SLICE_1670/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":0.000,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":1.878,
"delay":1.878
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":1.878,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- ------ --------------------- ------
CONSTRAINT 0.000 0.000 1
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 333
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141
NET DELAY 1.878 1.878 333
{top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_121/CLK top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_122/CLK}
CLOCK PIN 0.000 1.878 1
Uncertainty 0.000 1.878
Common Path Skew -0.041 1.837
Hold time 0.097 1.934
---------------------------------------- ------------------------ ---------------- ------ --------------------- ------
Required Time -1.934
Arrival Time 2.043
---------------------------------------- ------------------------ ---------------- ------ --------------------- ------
Path Slack (Passed) 0.109
++++ Path 2 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_136/Q (SLICE_R35C73C)
Path End : top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_120/DF (SLICE_R35C74D)
Source Clock : clk150 (R)
Destination Clock: clk150 (R)
Logic Level : 1
Delay Ratio : 47.3% (route), 52.7% (logic)
Clock Skew : 0.111 ns
Hold Constraint : 0.000 ns
Common Path Skew : -0.041 ns
Path Slack : 0.161 ns (Passed)
Source Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_136/CLK",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tu_1.SLICE_1674/CLK"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":1.767,
"delay":1.767
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":1.767,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- ------ --------------------- ------
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 333
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141
NET DELAY 1.767 1.767 333
{top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_136/CLK top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_141/CLK}
CLOCK PIN 0.000 1.767 1
Data Path
{
"path_begin":
{
"type":"pin",
"log_name":"top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_136/Q",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tu_1.SLICE_1674/Q0"
},
"path_end":
{
"type":"pin",
"log_name":"top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_120/DF",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tu_1.SLICE_1659/M1"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_136/CLK",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tu_1.SLICE_1674/CLK"
},
"pin1":
{
"log_name":"top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_136/Q",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tu_1.SLICE_1674/Q0"
},
"arrive":1.940,
"delay":0.173
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/trig_u/tu_1/secured_signal_13_136",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tu_1.Nc8pHcEsIxIrf"
},
"arrive":2.095,
"delay":0.155
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":2.095,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- ------ --------------------- ------
top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_136/CLK->top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_136/Q
SLICE_R35C73C REG_DEL 0.173 1.940 5
top_reveal_coretop_instance/core0/trig_u/tu_1/secured_signal_13_136
NET DELAY 0.155 2.095 5
top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_120/DF
ENDPOINT 0.000 2.095 1
Destination Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_119/CLK",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tu_1.SLICE_1659/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":0.000,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":1.878,
"delay":1.878
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":1.878,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- ------ --------------------- ------
CONSTRAINT 0.000 0.000 1
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 333
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141
NET DELAY 1.878 1.878 333
{top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_119/CLK top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_120/CLK}
CLOCK PIN 0.000 1.878 1
Uncertainty 0.000 1.878
Common Path Skew -0.041 1.837
Hold time 0.097 1.934
---------------------------------------- ------------------------ ---------------- ------ --------------------- ------
Required Time -1.934
Arrival Time 2.095
---------------------------------------- ------------------------ ---------------- ------ --------------------- ------
Path Slack (Passed) 0.161
++++ Path 3 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_132/Q (SLICE_R44C77D)
Path End : top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_116/DF (SLICE_R44C77B)
Source Clock : clk150 (R)
Destination Clock: clk150 (R)
Logic Level : 1
Delay Ratio : 32.6% (route), 67.4% (logic)
Clock Skew : 0.111 ns
Hold Constraint : 0.000 ns
Common Path Skew : -0.108 ns
Path Slack : 0.167 ns (Passed)
Source Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_132/CLK",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tu_3.SLICE_1525/CLK"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":1.767,
"delay":1.767
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":1.767,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- ------ --------------------- ------
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 333
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141
NET DELAY 1.767 1.767 333
{top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_132/CLK top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_133/CLK}
CLOCK PIN 0.000 1.767 1
Data Path
{
"path_begin":
{
"type":"pin",
"log_name":"top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_132/Q",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tu_3.SLICE_1525/Q0"
},
"path_end":
{
"type":"pin",
"log_name":"top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_116/DF",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tu_3.SLICE_1546/M1"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_132/CLK",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tu_3.SLICE_1525/CLK"
},
"pin1":
{
"log_name":"top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_132/Q",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tu_3.SLICE_1525/Q0"
},
"arrive":1.945,
"delay":0.178
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/trig_u/tu_3/secured_signal_11_132",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tu_3.Nc8pHcEsIxIrb"
},
"arrive":2.031,
"delay":0.086
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":2.031,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- ------ --------------------- ------
top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_132/CLK->top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_132/Q
SLICE_R44C77D REG_DEL 0.178 1.945 5
top_reveal_coretop_instance/core0/trig_u/tu_3/secured_signal_11_132
NET DELAY 0.086 2.031 5
top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_116/DF
ENDPOINT 0.000 2.031 1
Destination Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_115/CLK",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tu_3.SLICE_1546/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":0.000,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":1.878,
"delay":1.878
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":1.878,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- ------ --------------------- ------
CONSTRAINT 0.000 0.000 1
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 333
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141
NET DELAY 1.878 1.878 333
{top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_115/CLK top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_116/CLK}
CLOCK PIN 0.000 1.878 1
Uncertainty 0.000 1.878
Common Path Skew -0.108 1.770
Hold time 0.094 1.864
---------------------------------------- ------------------------ ---------------- ------ --------------------- ------
Required Time -1.864
Arrival Time 2.031
---------------------------------------- ------------------------ ---------------- ------ --------------------- ------
Path Slack (Passed) 0.167
++++ Path 4 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_138/Q (SLICE_R33C73C)
Path End : top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_122/DF (SLICE_R33C73D)
Source Clock : clk150 (R)
Destination Clock: clk150 (R)
Logic Level : 1
Delay Ratio : 32.6% (route), 67.4% (logic)
Clock Skew : 0.111 ns
Hold Constraint : 0.000 ns
Common Path Skew : -0.110 ns
Path Slack : 0.169 ns (Passed)
Source Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_138/CLK",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tu_1.SLICE_1678/CLK"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":1.767,
"delay":1.767
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":1.767,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- ------ --------------------- ------
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 333
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141
NET DELAY 1.767 1.767 333
{top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_138/CLK top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_142/CLK}
CLOCK PIN 0.000 1.767 1
Data Path
{
"path_begin":
{
"type":"pin",
"log_name":"top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_138/Q",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tu_1.SLICE_1678/Q0"
},
"path_end":
{
"type":"pin",
"log_name":"top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_122/DF",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tu_1.SLICE_1670/M1"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_138/CLK",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tu_1.SLICE_1678/CLK"
},
"pin1":
{
"log_name":"top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_138/Q",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tu_1.SLICE_1678/Q0"
},
"arrive":1.945,
"delay":0.178
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/trig_u/tu_1/secured_signal_13_138",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tu_1.Nc8pHcEsIxIrh"
},
"arrive":2.031,
"delay":0.086
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":2.031,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- ------ --------------------- ------
top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_138/CLK->top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_138/Q
SLICE_R33C73C REG_DEL 0.178 1.945 5
top_reveal_coretop_instance/core0/trig_u/tu_1/secured_signal_13_138
NET DELAY 0.086 2.031 5
top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_122/DF
ENDPOINT 0.000 2.031 1
Destination Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_121/CLK",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tu_1.SLICE_1670/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":0.000,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":1.878,
"delay":1.878
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":1.878,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- ------ --------------------- ------
CONSTRAINT 0.000 0.000 1
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 333
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141
NET DELAY 1.878 1.878 333
{top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_121/CLK top_reveal_coretop_instance/core0/trig_u/tu_1/secured_instance_13_122/CLK}
CLOCK PIN 0.000 1.878 1
Uncertainty 0.000 1.878
Common Path Skew -0.110 1.768
Hold time 0.094 1.862
---------------------------------------- ------------------------ ---------------- ------ --------------------- ------
Required Time -1.862
Arrival Time 2.031
---------------------------------------- ------------------------ ---------------- ------ --------------------- ------
Path Slack (Passed) 0.169
++++ Path 5 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : top_reveal_coretop_instance/core0/trig_u/tu_4/secured_instance_10_131/Q (SLICE_R43C84A)
Path End : top_reveal_coretop_instance/core0/trig_u/tu_4/secured_instance_10_115/DF (SLICE_R43C84B)
Source Clock : clk150 (R)
Destination Clock: clk150 (R)
Logic Level : 1
Delay Ratio : 32.6% (route), 67.4% (logic)
Clock Skew : 0.111 ns
Hold Constraint : 0.000 ns
Common Path Skew : -0.110 ns
Path Slack : 0.169 ns (Passed)
Source Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"top_reveal_coretop_instance/core0/trig_u/tu_4/secured_instance_10_131/CLK",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tu_4.SLICE_1473/CLK"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":1.767,
"delay":1.767
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":1.767,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- ------ --------------------- ------
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 333
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141
NET DELAY 1.767 1.767 333
{top_reveal_coretop_instance/core0/trig_u/tu_4/secured_instance_10_131/CLK top_reveal_coretop_instance/core0/trig_u/tu_4/secured_instance_10_139/CLK}
CLOCK PIN 0.000 1.767 1
Data Path
{
"path_begin":
{
"type":"pin",
"log_name":"top_reveal_coretop_instance/core0/trig_u/tu_4/secured_instance_10_131/Q",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tu_4.SLICE_1473/Q0"
},
"path_end":
{
"type":"pin",
"log_name":"top_reveal_coretop_instance/core0/trig_u/tu_4/secured_instance_10_115/DF",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tu_4.SLICE_1471/M0"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"top_reveal_coretop_instance/core0/trig_u/tu_4/secured_instance_10_131/CLK",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tu_4.SLICE_1473/CLK"
},
"pin1":
{
"log_name":"top_reveal_coretop_instance/core0/trig_u/tu_4/secured_instance_10_131/Q",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tu_4.SLICE_1473/Q0"
},
"arrive":1.945,
"delay":0.178
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/trig_u/tu_4/secured_signal_10_131",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tu_4.Nc8pHcEsIxIra"
},
"arrive":2.031,
"delay":0.086
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":2.031,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- ------ --------------------- ------
top_reveal_coretop_instance/core0/trig_u/tu_4/secured_instance_10_131/CLK->top_reveal_coretop_instance/core0/trig_u/tu_4/secured_instance_10_131/Q
SLICE_R43C84A REG_DEL 0.178 1.945 5
top_reveal_coretop_instance/core0/trig_u/tu_4/secured_signal_10_131
NET DELAY 0.086 2.031 5
top_reveal_coretop_instance/core0/trig_u/tu_4/secured_instance_10_115/DF
ENDPOINT 0.000 2.031 1
Destination Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"top_reveal_coretop_instance/core0/trig_u/tu_4/secured_instance_10_115/CLK",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tu_4.SLICE_1471/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":0.000,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":1.878,
"delay":1.878
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":1.878,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- ------ --------------------- ------
CONSTRAINT 0.000 0.000 1
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 333
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141
NET DELAY 1.878 1.878 333
{top_reveal_coretop_instance/core0/trig_u/tu_4/secured_instance_10_115/CLK top_reveal_coretop_instance/core0/trig_u/tu_4/secured_instance_10_116/CLK}
CLOCK PIN 0.000 1.878 1
Uncertainty 0.000 1.878
Common Path Skew -0.110 1.768
Hold time 0.094 1.862
---------------------------------------- ------------------------ ---------------- ------ --------------------- ------
Required Time -1.862
Arrival Time 2.031
---------------------------------------- ------------------------ ---------------- ------ --------------------- ------
Path Slack (Passed) 0.169
++++ Path 6 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_481/Q (SLICE_R42C83B)
Path End : top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_482/DF (SLICE_R42C83B)
Source Clock : clk150 (R)
Destination Clock: clk150 (R)
Logic Level : 1
Delay Ratio : 32.6% (route), 67.4% (logic)
Clock Skew : 0.111 ns
Hold Constraint : 0.000 ns
Common Path Skew : -0.110 ns
Path Slack : 0.169 ns (Passed)
Source Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_481/CLK",
"phy_name":"top_reveal_coretop_instance.core0.jtag_int_u.SLICE_637/CLK"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":1.767,
"delay":1.767
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":1.767,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- ------ --------------------- ------
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 333
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141
NET DELAY 1.767 1.767 333
{top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_481/CLK top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_482/CLK}
CLOCK PIN 0.000 1.767 1
Data Path
{
"path_begin":
{
"type":"pin",
"log_name":"top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_481/Q",
"phy_name":"top_reveal_coretop_instance.core0.jtag_int_u.SLICE_637/Q0"
},
"path_end":
{
"type":"pin",
"log_name":"top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_482/DF",
"phy_name":"top_reveal_coretop_instance.core0.jtag_int_u.SLICE_637/M1"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_481/CLK",
"phy_name":"top_reveal_coretop_instance.core0.jtag_int_u.SLICE_637/CLK"
},
"pin1":
{
"log_name":"top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_481/Q",
"phy_name":"top_reveal_coretop_instance.core0.jtag_int_u.SLICE_637/Q0"
},
"arrive":1.945,
"delay":0.178
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/jtag_int_u/secured_signal_2_162",
"phy_name":"top_reveal_coretop_instance.core0.jtag_int_u.Neo15zDnCIDBEJ3zgix1[0]"
},
"arrive":2.031,
"delay":0.086
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":2.031,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- ------ --------------------- ------
top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_481/CLK->top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_481/Q
SLICE_R42C83B REG_DEL 0.178 1.945 1
top_reveal_coretop_instance/core0/jtag_int_u/secured_signal_2_162
NET DELAY 0.086 2.031 1
top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_482/DF
ENDPOINT 0.000 2.031 1
Destination Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_481/CLK",
"phy_name":"top_reveal_coretop_instance.core0.jtag_int_u.SLICE_637/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":0.000,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":1.878,
"delay":1.878
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":1.878,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- ------ --------------------- ------
CONSTRAINT 0.000 0.000 1
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 333
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141
NET DELAY 1.878 1.878 333
{top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_481/CLK top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_482/CLK}
CLOCK PIN 0.000 1.878 1
Uncertainty 0.000 1.878
Common Path Skew -0.110 1.768
Hold time 0.094 1.862
---------------------------------------- ------------------------ ---------------- ------ --------------------- ------
Required Time -1.862
Arrival Time 2.031
---------------------------------------- ------------------------ ---------------- ------ --------------------- ------
Path Slack (Passed) 0.169
++++ Path 7 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : top_reveal_coretop_instance/core0/trig_u/tu_2/secured_instance_12_146/Q (SLICE_R41C77C)
Path End : top_reveal_coretop_instance/core0/trig_u/tu_2/secured_instance_12_130/DF (SLICE_R41C77D)
Source Clock : clk150 (R)
Destination Clock: clk150 (R)
Logic Level : 1
Delay Ratio : 32.5% (route), 67.5% (logic)
Clock Skew : 0.111 ns
Hold Constraint : 0.000 ns
Common Path Skew : -0.110 ns
Path Slack : 0.170 ns (Passed)
Source Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"top_reveal_coretop_instance/core0/trig_u/tu_2/secured_instance_12_140/CLK",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tu_2.SLICE_1603/CLK"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":1.767,
"delay":1.767
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":1.767,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- ------ --------------------- ------
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 333
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141
NET DELAY 1.767 1.767 333
{top_reveal_coretop_instance/core0/trig_u/tu_2/secured_instance_12_140/CLK top_reveal_coretop_instance/core0/trig_u/tu_2/secured_instance_12_146/CLK}
CLOCK PIN 0.000 1.767 1
Data Path
{
"path_begin":
{
"type":"pin",
"log_name":"top_reveal_coretop_instance/core0/trig_u/tu_2/secured_instance_12_146/Q",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tu_2.SLICE_1603/Q1"
},
"path_end":
{
"type":"pin",
"log_name":"top_reveal_coretop_instance/core0/trig_u/tu_2/secured_instance_12_130/DF",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tu_2.SLICE_1595/M1"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"top_reveal_coretop_instance/core0/trig_u/tu_2/secured_instance_12_146/CLK",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tu_2.SLICE_1603/CLK"
},
"pin1":
{
"log_name":"top_reveal_coretop_instance/core0/trig_u/tu_2/secured_instance_12_146/Q",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tu_2.SLICE_1603/Q1"
},
"arrive":1.946,
"delay":0.179
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/trig_u/tu_2/secured_signal_12_146",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tu_2.NoxeB5huJp20Cv"
},
"arrive":2.032,
"delay":0.086
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":2.032,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- ------ --------------------- ------
top_reveal_coretop_instance/core0/trig_u/tu_2/secured_instance_12_146/CLK->top_reveal_coretop_instance/core0/trig_u/tu_2/secured_instance_12_146/Q
SLICE_R41C77C REG_DEL 0.179 1.946 5
top_reveal_coretop_instance/core0/trig_u/tu_2/secured_signal_12_146
NET DELAY 0.086 2.032 5
top_reveal_coretop_instance/core0/trig_u/tu_2/secured_instance_12_130/DF
ENDPOINT 0.000 2.032 1
Destination Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"top_reveal_coretop_instance/core0/trig_u/tu_2/secured_instance_12_129/CLK",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tu_2.SLICE_1595/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":0.000,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":1.878,
"delay":1.878
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":1.878,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- ------ --------------------- ------
CONSTRAINT 0.000 0.000 1
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 333
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141
NET DELAY 1.878 1.878 333
{top_reveal_coretop_instance/core0/trig_u/tu_2/secured_instance_12_129/CLK top_reveal_coretop_instance/core0/trig_u/tu_2/secured_instance_12_130/CLK}
CLOCK PIN 0.000 1.878 1
Uncertainty 0.000 1.878
Common Path Skew -0.110 1.768
Hold time 0.094 1.862
---------------------------------------- ------------------------ ---------------- ------ --------------------- ------
Required Time -1.862
Arrival Time 2.032
---------------------------------------- ------------------------ ---------------- ------ --------------------- ------
Path Slack (Passed) 0.170
++++ Path 8 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : top_reveal_coretop_instance/core0/trig_u/tu_2/secured_instance_12_144/Q (SLICE_R41C73D)
Path End : top_reveal_coretop_instance/core0/trig_u/tu_2/secured_instance_12_128/DF (SLICE_R41C73C)
Source Clock : clk150 (R)
Destination Clock: clk150 (R)
Logic Level : 1
Delay Ratio : 32.5% (route), 67.5% (logic)
Clock Skew : 0.111 ns
Hold Constraint : 0.000 ns
Common Path Skew : -0.110 ns
Path Slack : 0.170 ns (Passed)
Source Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"top_reveal_coretop_instance/core0/trig_u/tu_2/secured_instance_12_143/CLK",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tu_2.IbvqsJxiwzrIDIH7[12].SLICE_932/CLK"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":1.767,
"delay":1.767
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":1.767,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- ------ --------------------- ------
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 333
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141
NET DELAY 1.767 1.767 333
{top_reveal_coretop_instance/core0/trig_u/tu_2/secured_instance_12_143/CLK top_reveal_coretop_instance/core0/trig_u/tu_2/secured_instance_12_144/CLK}
CLOCK PIN 0.000 1.767 1
Data Path
{
"path_begin":
{
"type":"pin",
"log_name":"top_reveal_coretop_instance/core0/trig_u/tu_2/secured_instance_12_144/Q",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tu_2.IbvqsJxiwzrIDIH7[12].SLICE_932/Q1"
},
"path_end":
{
"type":"pin",
"log_name":"top_reveal_coretop_instance/core0/trig_u/tu_2/secured_instance_12_128/DF",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tu_2.SLICE_1594/M1"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"top_reveal_coretop_instance/core0/trig_u/tu_2/secured_instance_12_144/CLK",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tu_2.IbvqsJxiwzrIDIH7[12].SLICE_932/CLK"
},
"pin1":
{
"log_name":"top_reveal_coretop_instance/core0/trig_u/tu_2/secured_instance_12_144/Q",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tu_2.IbvqsJxiwzrIDIH7[12].SLICE_932/Q1"
},
"arrive":1.946,
"delay":0.179
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/trig_u/tu_2/secured_signal_12_144",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tu_2.NoxeB5huJp20Ct"
},
"arrive":2.032,
"delay":0.086
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":2.032,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- ------ --------------------- ------
top_reveal_coretop_instance/core0/trig_u/tu_2/secured_instance_12_144/CLK->top_reveal_coretop_instance/core0/trig_u/tu_2/secured_instance_12_144/Q
SLICE_R41C73D REG_DEL 0.179 1.946 5
top_reveal_coretop_instance/core0/trig_u/tu_2/secured_signal_12_144
NET DELAY 0.086 2.032 5
top_reveal_coretop_instance/core0/trig_u/tu_2/secured_instance_12_128/DF
ENDPOINT 0.000 2.032 1
Destination Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"top_reveal_coretop_instance/core0/trig_u/tu_2/secured_instance_12_127/CLK",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tu_2.SLICE_1594/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":0.000,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":1.878,
"delay":1.878
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":1.878,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- ------ --------------------- ------
CONSTRAINT 0.000 0.000 1
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 333
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141
NET DELAY 1.878 1.878 333
{top_reveal_coretop_instance/core0/trig_u/tu_2/secured_instance_12_127/CLK top_reveal_coretop_instance/core0/trig_u/tu_2/secured_instance_12_128/CLK}
CLOCK PIN 0.000 1.878 1
Uncertainty 0.000 1.878
Common Path Skew -0.110 1.768
Hold time 0.094 1.862
---------------------------------------- ------------------------ ---------------- ------ --------------------- ------
Required Time -1.862
Arrival Time 2.032
---------------------------------------- ------------------------ ---------------- ------ --------------------- ------
Path Slack (Passed) 0.170
++++ Path 9 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_146/Q (SLICE_R45C75D)
Path End : top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_130/DF (SLICE_R45C75C)
Source Clock : clk150 (R)
Destination Clock: clk150 (R)
Logic Level : 1
Delay Ratio : 32.5% (route), 67.5% (logic)
Clock Skew : 0.111 ns
Hold Constraint : 0.000 ns
Common Path Skew : -0.110 ns
Path Slack : 0.170 ns (Passed)
Source Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_140/CLK",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tu_3.SLICE_1522/CLK"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":1.767,
"delay":1.767
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":1.767,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- ------ --------------------- ------
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 333
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141
NET DELAY 1.767 1.767 333
{top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_140/CLK top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_146/CLK}
CLOCK PIN 0.000 1.767 1
Data Path
{
"path_begin":
{
"type":"pin",
"log_name":"top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_146/Q",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tu_3.SLICE_1522/Q1"
},
"path_end":
{
"type":"pin",
"log_name":"top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_130/DF",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tu_3.SLICE_1530/M1"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_146/CLK",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tu_3.SLICE_1522/CLK"
},
"pin1":
{
"log_name":"top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_146/Q",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tu_3.SLICE_1522/Q1"
},
"arrive":1.946,
"delay":0.179
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/trig_u/tu_3/secured_signal_11_146",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tu_3.NoxeB5huJp20Cv"
},
"arrive":2.032,
"delay":0.086
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":2.032,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- ------ --------------------- ------
top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_146/CLK->top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_146/Q
SLICE_R45C75D REG_DEL 0.179 1.946 5
top_reveal_coretop_instance/core0/trig_u/tu_3/secured_signal_11_146
NET DELAY 0.086 2.032 5
top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_130/DF
ENDPOINT 0.000 2.032 1
Destination Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_129/CLK",
"phy_name":"top_reveal_coretop_instance.core0.trig_u.tu_3.SLICE_1530/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":0.000,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":1.878,
"delay":1.878
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":1.878,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- ------ --------------------- ------
CONSTRAINT 0.000 0.000 1
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 333
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141
NET DELAY 1.878 1.878 333
{top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_129/CLK top_reveal_coretop_instance/core0/trig_u/tu_3/secured_instance_11_130/CLK}
CLOCK PIN 0.000 1.878 1
Uncertainty 0.000 1.878
Common Path Skew -0.110 1.768
Hold time 0.094 1.862
---------------------------------------- ------------------------ ---------------- ------ --------------------- ------
Required Time -1.862
Arrival Time 2.032
---------------------------------------- ------------------------ ---------------- ------ --------------------- ------
Path Slack (Passed) 0.170
++++ Path 10 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Path Begin : top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_483/Q (SLICE_R35C82B)
Path End : top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_484/DF (SLICE_R35C82B)
Source Clock : clk150 (R)
Destination Clock: clk150 (R)
Logic Level : 1
Delay Ratio : 32.5% (route), 67.5% (logic)
Clock Skew : 0.111 ns
Hold Constraint : 0.000 ns
Common Path Skew : -0.110 ns
Path Slack : 0.170 ns (Passed)
Source Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_484/CLK",
"phy_name":"top_reveal_coretop_instance.core0.jtag_int_u.SLICE_1259/CLK"
},
"path_sections":[
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":1.767,
"delay":1.767
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":1.767,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- ------ --------------------- ------
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 333
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141
NET DELAY 1.767 1.767 333
{top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_484/CLK top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_483/CLK}
CLOCK PIN 0.000 1.767 1
Data Path
{
"path_begin":
{
"type":"pin",
"log_name":"top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_483/Q",
"phy_name":"top_reveal_coretop_instance.core0.jtag_int_u.SLICE_1259/Q1"
},
"path_end":
{
"type":"pin",
"log_name":"top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_484/DF",
"phy_name":"top_reveal_coretop_instance.core0.jtag_int_u.SLICE_1259/M0"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_483/CLK",
"phy_name":"top_reveal_coretop_instance.core0.jtag_int_u.SLICE_1259/CLK"
},
"pin1":
{
"log_name":"top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_483/Q",
"phy_name":"top_reveal_coretop_instance.core0.jtag_int_u.SLICE_1259/Q1"
},
"arrive":1.946,
"delay":0.179
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/jtag_int_u/secured_signal_2_160",
"phy_name":"top_reveal_coretop_instance.core0.jtag_int_u.Neo15zDnCIDBEJ3zgix1[2]"
},
"arrive":2.032,
"delay":0.086
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":2.032,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- ------ --------------------- ------
top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_483/CLK->top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_483/Q
SLICE_R35C82B REG_DEL 0.179 1.946 2
top_reveal_coretop_instance/core0/jtag_int_u/secured_signal_2_160
NET DELAY 0.086 2.032 2
top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_484/DF
ENDPOINT 0.000 2.032 1
Destination Clock Path
{
"path_begin":
{
"type":"pin",
"log_name":"OSCA001.OSCA_inst/HFCLKOUT",
"phy_name":"OSCA001.OSCA_inst/HFCLKOUT"
},
"path_end":
{
"type":"pin",
"log_name":"top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_484/CLK",
"phy_name":"top_reveal_coretop_instance.core0.jtag_int_u.SLICE_1259/CLK"
},
"path_sections":[
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":0.000,
"delay":0.000
},
{
"type":"net_delay",
"net":
{
"log_name":"top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141",
"phy_name":"clk150"
},
"arrive":1.878,
"delay":1.878
},
{
"type":"site_delay",
"pin0":
{
"log_name":"",
"phy_name":""
},
"pin1":
{
"log_name":"",
"phy_name":""
},
"arrive":1.878,
"delay":0.000
}
]
}
Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout
---------------------------------------- ------------------------ ---------------- ------ --------------------- ------
CONSTRAINT 0.000 0.000 1
OSCA001.OSCA_inst/HFCLKOUT OSC_CORE_OSC_CORE_R1C137 CLOCK LATENCY 0.000 0.000 333
top_reveal_coretop_instance/core0/tm_u/secured_instance_1_107/secured_signal_0_141
NET DELAY 1.878 1.878 333
{top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_484/CLK top_reveal_coretop_instance/core0/jtag_int_u/secured_instance_2_483/CLK}
CLOCK PIN 0.000 1.878 1
Uncertainty 0.000 1.878
Common Path Skew -0.110 1.768
Hold time 0.094 1.862
---------------------------------------- ------------------------ ---------------- ------ --------------------- ------
Required Time -1.862
Arrival Time 2.032
---------------------------------------- ------------------------ ---------------- ------ --------------------- ------
Path Slack (Passed) 0.170
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
End of Detailed Report for timing paths
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
##########################################################