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Tool: Synplify Pro (R)
Build: U-2023.03LR-1
Install: C:\lscc\radiant\2023.1\synpbase
OS: Windows 10 or later
Hostname: DESKTOP-CQ0R02Q

Implementation : impl1

# Written on Fri Dec  1 10:23:29 2023

##### DESIGN INFO #######################################################

Top View:                "Top"
Constraint File(s):      "D:\02_LSCC\09_GSR\Final\LAB04_GSR_LSR\source\impl1\timingsdc.sdc"




##### SUMMARY ############################################################

Found 0 issues in 0 out of 2 constraints


##### DETAILS ############################################################



Clock Relationships
*******************

Starting     Ending     |     rise to rise     |     fall to fall     |     rise to fall     |     fall to rise                     
-----------------------------------------------------------------------------------------------------------------------------------
CLK1         CLK1       |     6.667            |     No paths         |     No paths         |     No paths                         
clk2         clk2       |     6.667            |     No paths         |     No paths         |     No paths                         
===================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.


Unconstrained Start/End Points
******************************

p:G_reset
p:LED1
p:LED2
p:reset


Inapplicable constraints
************************

(none)


Applicable constraints with issues
**********************************

(none)


Constraints with matching wildcard expressions
**********************************************

(none)


Library Report
**************


# End of Constraint Checker Report