Project Settings
Project Name proj_1 Device Name impl_1: Lattice LFCPNX : LFCPNX_100
Implementation Name impl_1 Top Module Top
Pipelining 1 Retiming 0
Resource Sharing 1 Fanout Guide 1000
Disable I/O Insertion 0 Disable Sequential Optimizations 0
Clock Conversion 0 FSM Compiler 1

Run Status
Job Name Status CPU Time Real Time Memory Date/Time
(compiler)Complete 74 1 0 - 00m:03s - 2023-11-21
5:56 PM
(premap)Complete 5 1 0 0m:00s 0m:01s 198MB 2023-11-21
5:56 PM
(fpga_mapper)Complete 8 1 0 0m:01s 0m:02s 201MB 2023-11-21
5:56 PM
Multi-srs Generator Complete2023-11-21
5:56 PM

Area Summary
Register bits 3 I/O cells 4
Block RAMs (v_ram) 0 DSPs (dsp_used) 0
LUTs (total_luts) 1

Timing Summary
Clock NameReq FreqEst FreqSlack
Top|CLK1200.0 MHz765.1 MHz3.693

Optimizations Summary
Combined Clock Conversion 1 / 0