Timing Report
Lattice Timing Report -  Setup  and Hold, Version Radiant Software (64-bit) 2023.1.1.200.1

Fri Dec  1 10:24:02 2023

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2023 Lattice Semiconductor Corporation,  All rights reserved.

Command line:    timing -sethld -v 10 -u 10 -endpoints 10 -nperend 1 -sp 9_High-Performance_1.0V -hsp m -pwrprd -html -rpt LAB04_impl1.twr LAB04_impl1.udb -gui

-------------------------------------------
Design:          Top
Family:          LFCPNX
Device:          LFCPNX-100
Package:         LFG672
Performance:     9_High-Performance_1.0V
Package Status:                     Final          Version 16
Performance Hardware Data Status :   Final Version 3.9
-------------------------------------------


=====================================================================
                    Table of Contents
=====================================================================
  • 1 DESIGN CHECKING
  • 1.1 SDC Constraints
  • 1.2 Constraint Coverage
  • 1.3 Overall Summary
  • 1.4 Unconstrained Report
  • 1.5 Combinational Loop
  • 2 Setup at Speed Grade 9_High-Performance_1.0V Corner at 85 Degrees
  • 2.1 Clock Summary
  • 2.2 Endpoint slacks
  • 2.3 Detailed Report
  • 3 Hold at Speed Grade m Corner at 0 Degrees
  • 3.1 Endpoint slacks
  • 3.2 Detailed Report
  • ===================================================================== End of Table of Contents ===================================================================== 1 DESIGN CHECKING 1.1 SDC Constraints create_clock -name {CLK1} -period 6.667 -waveform {0.000 3.333} [get_ports CLK1] create_clock -name {clk2} -period 6.667 -waveform {0.000 3.333} [get_ports clk2] 1.2 Constraint Coverage Constraint Coverage: 94.8276% 1.3 Overall Summary Setup at Speed Grade 9_High-Performance_1.0V Corner at 85 Degrees Timing Errors: 0 endpoints; Total Negative Slack: 0.000 ns Hold at Speed Grade m Corner at 0 Degrees Timing Errors: 0 endpoints; Total Negative Slack: 0.000 ns 1.4 Unconstrained Report 1.4.1 Unconstrained Start/End Points Clocked but unconstrained timing start points ------------------------------------------------------------------- Listing 2 Start Points | Type ------------------------------------------------------------------- LED2_0io.PIC_inst/Q | No required time LED1_0io.PIC_inst/Q | No required time ------------------------------------------------------------------- | Number of unconstrained timing start po | ints | 2 | ------------------------------------------------------------------- Clocked but unconstrained timing end points ------------------------------------------------------------------- Listing 2 End Points | Type ------------------------------------------------------------------- {RST002/Rst_Sync1_reg.ff_inst/LSR RST002/Rst_Sync.ff_inst/LSR} | No arrival time {RST001/Rst_Sync1_reg.ff_inst/LSR RST001/Rst_Sync.ff_inst/LSR} | No arrival time ------------------------------------------------------------------- | Number of unconstrained timing end poin | ts | 2 | ------------------------------------------------------------------- 1.4.2 Start/End Points Without Timing Constraints I/O ports without constraint ---------------------------- Possible constraints to use on I/O ports are: set_input_delay, set_output_delay, set_max_delay, create_clock, create_generated_clock, ... ------------------------------------------------------------------- Listing 3 Start or End Points | Type ------------------------------------------------------------------- reset | input LED2 | output LED1 | output ------------------------------------------------------------------- | Number of I/O ports without constraint | 3 | ------------------------------------------------------------------- Nets without clock definition Define a clock on a top level port or a generated clock on a clock divider pin associated with this net(s). -------------------------------------------------- There is no instance satisfying reporting criteria 1.5 Combinational Loop None 2 Setup at Speed Grade 9_High-Performance_1.0V Corner at 85 Degrees 2.1 Clock Summary 2.1.1 Clock "CLK1" create_clock -name {CLK1} -period 6.667 -waveform {0.000 3.333} [get_ports CLK1] Single Clock Domain ------------------------------------------------------------------------------------------------------- Clock CLK1 | | Period | Frequency ------------------------------------------------------------------------------------------------------- From CLK1 | Target | 6.667 ns | 149.993 MHz | Actual (all paths) | 5.306 ns | 188.466 MHz CLK1_pad.bb_inst/B (MPW) | (50% duty cycle) | 5.000 ns | 200.000 MHz ------------------------------------------------------------------------------------------------------- Clock Domain Crossing ------------------------------------------------------------------------------------------------------ Clock CLK1 | Worst Time Between Edges | Comment ------------------------------------------------------------------------------------------------------ From clk2 | ---- | No path ------------------------------------------------------------------------------------------------------ 2.1.2 Clock "clk2" create_clock -name {clk2} -period 6.667 -waveform {0.000 3.333} [get_ports clk2] Single Clock Domain ------------------------------------------------------------------------------------------------------- Clock clk2 | | Period | Frequency ------------------------------------------------------------------------------------------------------- From clk2 | Target | 6.667 ns | 149.993 MHz | Actual (all paths) | 5.000 ns | 200.000 MHz clk2_pad.bb_inst/B (MPW) | (50% duty cycle) | 5.000 ns | 200.000 MHz ------------------------------------------------------------------------------------------------------- Clock Domain Crossing ------------------------------------------------------------------------------------------------------ Clock clk2 | Worst Time Between Edges | Comment ------------------------------------------------------------------------------------------------------ From CLK1 | ---- | No path ------------------------------------------------------------------------------------------------------ 2.2 Endpoint slacks ------------------------------------------------------- Listing 10 End Points | Slack ------------------------------------------------------- LED1_0io.PIC_inst/D | 1.361 ns LED2_0io.PIC_inst/D | 3.219 ns CNT01/Couti[0].ff_inst/LSR | 3.676 ns CNT01/Couti[15].ff_inst/LSR | 3.676 ns {CNT01/Couti_reg[3].ff_inst/LSR CNT01/Couti_reg[4].ff_inst/LSR} | 3.801 ns {CNT01/Couti_reg[5].ff_inst/LSR CNT01/Couti_reg[6].ff_inst/LSR} | 3.801 ns {CNT01/Couti_reg[7].ff_inst/LSR CNT01/Couti_reg[8].ff_inst/LSR} | 3.801 ns {CNT01/Couti_reg[9].ff_inst/LSR CNT01/Couti_reg[10].ff_inst/LSR} | 3.801 ns {CNT01/Couti_reg[11].ff_inst/LSR CNT01/Couti_reg[12].ff_inst/LSR} | 3.801 ns {CNT01/Couti_reg[13].ff_inst/LSR CNT01/Couti_reg[14].ff_inst/LSR} | 3.801 ns ------------------------------------------------------- | Setup # of endpoints with negative slack:| 0 | ------------------------------------------------------- 2.3 Detailed Report XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX Detail report of critical paths XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Detailed Report for timing paths +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ ++++Path 1 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : CNT01/Couti[15].ff_inst/Q (SLICE_R14C14A) Path End : LED1_0io.PIC_inst/D (SIOLOGIC_CORE_IOL_R28B) Source Clock : CLK1 (R) Destination Clock: CLK1 (R) Logic Level : 2 Delay Ratio : 89.9% (route), 10.1% (logic) Clock Skew : 0.084 ns Setup Constraint : 6.667 ns Path Slack : 1.361 ns (Passed) Source Clock Path { "path_begin": { "type":"port", "log_name":"CLK1", "phy_name":"CLK1" }, "path_end": { "type":"pin", "log_name":"CNT01/Couti[15].ff_inst/CLK", "phy_name":"CNT01.SLICE_0/CLK" }, "path_sections":[ { "type":"net_delay", "net": { "log_name":"CLK1", "phy_name":"CLK1" }, "arrive":0.000, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"CLK1_pad.bb_inst/B", "phy_name":"CLK1_pad.bb_inst/IOPAD" }, "pin1": { "log_name":"CLK1_pad.bb_inst/O", "phy_name":"CLK1_pad.bb_inst/PADDI" }, "arrive":1.366, "delay":1.366 }, { "type":"net_delay", "net": { "log_name":"RST001/CLK1_c", "phy_name":"CLK1_c" }, "arrive":4.002, "delay":2.636 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":4.002, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- --------------- ------------- -------- --------------------- ------ CLK1 Top CLOCK LATENCY 0.000 0.000 1 CLK1 NET DELAY 0.000 0.000 1 CLK1_pad.bb_inst/B->CLK1_pad.bb_inst/O SEIO33_CORE_P24 PADI_DEL 1.366 1.366 11 RST001/CLK1_c NET DELAY 2.636 4.002 11 CNT01/Couti[15].ff_inst/CLK 0.000 4.002 1 Data Path { "path_begin": { "type":"pin", "log_name":"CNT01/Couti[15].ff_inst/Q", "phy_name":"CNT01.SLICE_0/Q0" }, "path_end": { "type":"pin", "log_name":"LED1_0io.PIC_inst/D", "phy_name":"LED1_pad.bb_inst_IOL/TXDATA0" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"CNT01/Couti[15].ff_inst/CLK", "phy_name":"CNT01.SLICE_0/CLK" }, "pin1": { "log_name":"CNT01/Couti[15].ff_inst/Q", "phy_name":"CNT01.SLICE_0/Q0" }, "arrive":4.306, "delay":0.304 }, { "type":"net_delay", "net": { "log_name":"CNT01/CNT1_15", "phy_name":"CNT1[15]" }, "arrive":6.619, "delay":2.313 }, { "type":"site_delay", "pin0": { "log_name":"LED1_2_cZ/B", "phy_name":"SLICE_24/B0" }, "pin1": { "log_name":"LED1_2_cZ/Z", "phy_name":"SLICE_24/F0" }, "arrive":6.832, "delay":0.213 }, { "type":"net_delay", "net": { "log_name":"LED1_2", "phy_name":"LED1_2" }, "arrive":9.098, "delay":2.266 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":9.098, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- --------------- ------------- -------- --------------------- ------ CNT01/Couti[15].ff_inst/CLK->CNT01/Couti[15].ff_inst/Q SLICE_R14C14A REG_DEL 0.304 4.306 2 CNT01/CNT1_15 NET DELAY 2.313 6.619 2 LED1_2_cZ/B->LED1_2_cZ/Z SLICE_R27C83D CTOF_DEL 0.213 6.832 1 LED1_2 NET DELAY 2.266 9.098 1 LED1_0io.PIC_inst/D 0.000 9.098 1 Destination Clock Path { "path_begin": { "type":"port", "log_name":"CLK1", "phy_name":"CLK1" }, "path_end": { "type":"pin", "log_name":"LED1_0io.PIC_inst/CLK", "phy_name":"LED1_pad.bb_inst_IOL/SCLKOUT" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":6.667, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"CLK1", "phy_name":"CLK1" }, "arrive":6.667, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"CLK1_pad.bb_inst/B", "phy_name":"CLK1_pad.bb_inst/IOPAD" }, "pin1": { "log_name":"CLK1_pad.bb_inst/O", "phy_name":"CLK1_pad.bb_inst/PADDI" }, "arrive":8.033, "delay":1.366 }, { "type":"net_delay", "net": { "log_name":"RST001/CLK1_c", "phy_name":"CLK1_c" }, "arrive":10.753, "delay":2.720 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":10.753, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- --------------- ------------- -------- --------------------- ------ CONSTRAINT 0.000 6.667 1 CLK1 Top CLOCK LATENCY 0.000 6.667 1 CLK1 NET DELAY 0.000 6.667 1 CLK1_pad.bb_inst/B->CLK1_pad.bb_inst/O SEIO33_CORE_P24 PADI_DEL 1.366 8.033 11 RST001/CLK1_c NET DELAY 2.720 10.753 11 LED1_0io.PIC_inst/CLK 0.000 10.753 1 Uncertainty -(0.000) 10.753 Setup time -(0.294) 10.459 ---------------------------------------- --------------- ------------- -------- --------------------- ------ Required Time 10.459 Arrival Time -(9.098) ---------------------------------------- --------------- ------------- -------- --------------------- ------ Path Slack (Passed) 1.361 ++++ Path 2 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : CNT02/Couti[0].ff_inst/Q (SLICE_R30C83D) Path End : LED2_0io.PIC_inst/D (SIOLOGIC_CORE_IOL_R28A) Source Clock : clk2 (R) Destination Clock: clk2 (R) Logic Level : 2 Delay Ratio : 84.0% (route), 16.0% (logic) Clock Skew : 0.084 ns Setup Constraint : 6.667 ns Path Slack : 3.219 ns (Passed) Source Clock Path { "path_begin": { "type":"port", "log_name":"clk2", "phy_name":"clk2" }, "path_end": { "type":"pin", "log_name":"CNT02/Couti[0].ff_inst/CLK", "phy_name":"CNT02.SLICE_23/CLK" }, "path_sections":[ { "type":"net_delay", "net": { "log_name":"clk2", "phy_name":"clk2" }, "arrive":0.000, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"clk2_pad.bb_inst/B", "phy_name":"clk2_pad.bb_inst/IOPAD" }, "pin1": { "log_name":"clk2_pad.bb_inst/O", "phy_name":"clk2_pad.bb_inst/PADDI" }, "arrive":1.366, "delay":1.366 }, { "type":"net_delay", "net": { "log_name":"RST002/clk2_c", "phy_name":"clk2_c" }, "arrive":3.865, "delay":2.499 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":3.865, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- --------------- ------------- -------- --------------------- ------ clk2 Top CLOCK LATENCY 0.000 0.000 1 clk2 NET DELAY 0.000 0.000 1 clk2_pad.bb_inst/B->clk2_pad.bb_inst/O SEIO33_CORE_P22 PADI_DEL 1.366 1.366 11 RST002/clk2_c NET DELAY 2.499 3.865 11 CNT02/Couti[0].ff_inst/CLK 0.000 3.865 1 Data Path { "path_begin": { "type":"pin", "log_name":"CNT02/Couti[0].ff_inst/Q", "phy_name":"CNT02.SLICE_23/Q0" }, "path_end": { "type":"pin", "log_name":"LED2_0io.PIC_inst/D", "phy_name":"LED2_pad.bb_inst_IOL/TXDATA0" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"CNT02/Couti[0].ff_inst/CLK", "phy_name":"CNT02.SLICE_23/CLK" }, "pin1": { "log_name":"CNT02/Couti[0].ff_inst/Q", "phy_name":"CNT02.SLICE_23/Q0" }, "arrive":4.169, "delay":0.304 }, { "type":"net_delay", "net": { "log_name":"CNT02/CNT2_0", "phy_name":"CNT2[0]" }, "arrive":4.623, "delay":0.454 }, { "type":"site_delay", "pin0": { "log_name":"LED2_1_cZ/A", "phy_name":"SLICE_24/B1" }, "pin1": { "log_name":"LED2_1_cZ/Z", "phy_name":"SLICE_24/F1" }, "arrive":4.836, "delay":0.213 }, { "type":"net_delay", "net": { "log_name":"LED2_1", "phy_name":"LED2_1" }, "arrive":7.103, "delay":2.267 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":7.103, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- --------------- ------------- -------- --------------------- ------ CNT02/Couti[0].ff_inst/CLK->CNT02/Couti[0].ff_inst/Q SLICE_R30C83D REG_DEL 0.304 4.169 3 CNT02/CNT2_0 NET DELAY 0.454 4.623 3 LED2_1_cZ/A->LED2_1_cZ/Z SLICE_R27C83D CTOF_DEL 0.213 4.836 1 LED2_1 NET DELAY 2.267 7.103 1 LED2_0io.PIC_inst/D 0.000 7.103 1 Destination Clock Path { "path_begin": { "type":"port", "log_name":"clk2", "phy_name":"clk2" }, "path_end": { "type":"pin", "log_name":"LED2_0io.PIC_inst/CLK", "phy_name":"LED2_pad.bb_inst_IOL/SCLKOUT" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":6.667, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"clk2", "phy_name":"clk2" }, "arrive":6.667, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"clk2_pad.bb_inst/B", "phy_name":"clk2_pad.bb_inst/IOPAD" }, "pin1": { "log_name":"clk2_pad.bb_inst/O", "phy_name":"clk2_pad.bb_inst/PADDI" }, "arrive":8.033, "delay":1.366 }, { "type":"net_delay", "net": { "log_name":"RST002/clk2_c", "phy_name":"clk2_c" }, "arrive":10.616, "delay":2.583 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":10.616, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- --------------- ------------- -------- --------------------- ------ CONSTRAINT 0.000 6.667 1 clk2 Top CLOCK LATENCY 0.000 6.667 1 clk2 NET DELAY 0.000 6.667 1 clk2_pad.bb_inst/B->clk2_pad.bb_inst/O SEIO33_CORE_P22 PADI_DEL 1.366 8.033 11 RST002/clk2_c NET DELAY 2.583 10.616 11 LED2_0io.PIC_inst/CLK 0.000 10.616 1 Uncertainty -(0.000) 10.616 Setup time -(0.294) 10.322 ---------------------------------------- --------------- ------------- -------- --------------------- ------ Required Time 10.322 Arrival Time -(7.103) ---------------------------------------- --------------- ------------- -------- --------------------- ------ Path Slack (Passed) 3.219 ++++ Path 3 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : RST001/Rst_Sync.ff_inst/Q (SLICE_R27C83D) Path End : CNT01/Couti[0].ff_inst/LSR (SLICE_R14C14D) Source Clock : CLK1 (R) Destination Clock: CLK1 (R) Logic Level : 1 Delay Ratio : 89.0% (route), 11.0% (logic) Clock Skew : 0.000 ns Setup Constraint : 6.667 ns Path Slack : 3.676 ns (Passed) Source Clock Path { "path_begin": { "type":"port", "log_name":"CLK1", "phy_name":"CLK1" }, "path_end": { "type":"pin", "log_name":"RST001/Rst_Sync1_reg.ff_inst/CLK", "phy_name":"SLICE_24/CLK" }, "path_sections":[ { "type":"net_delay", "net": { "log_name":"CLK1", "phy_name":"CLK1" }, "arrive":0.000, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"CLK1_pad.bb_inst/B", "phy_name":"CLK1_pad.bb_inst/IOPAD" }, "pin1": { "log_name":"CLK1_pad.bb_inst/O", "phy_name":"CLK1_pad.bb_inst/PADDI" }, "arrive":1.366, "delay":1.366 }, { "type":"net_delay", "net": { "log_name":"RST001/CLK1_c", "phy_name":"CLK1_c" }, "arrive":4.002, "delay":2.636 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":4.002, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- --------------- ------------- -------- --------------------- ------ CLK1 Top CLOCK LATENCY 0.000 0.000 1 CLK1 NET DELAY 0.000 0.000 1 CLK1_pad.bb_inst/B->CLK1_pad.bb_inst/O SEIO33_CORE_P24 PADI_DEL 1.366 1.366 11 RST001/CLK1_c NET DELAY 2.636 4.002 11 {RST001/Rst_Sync1_reg.ff_inst/CLK RST001/Rst_Sync.ff_inst/CLK} 0.000 4.002 1 Data Path { "path_begin": { "type":"pin", "log_name":"RST001/Rst_Sync.ff_inst/Q", "phy_name":"SLICE_24/Q1" }, "path_end": { "type":"pin", "log_name":"CNT01/Couti[0].ff_inst/LSR", "phy_name":"CNT01.SLICE_22/LSR" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"RST001/Rst_Sync.ff_inst/CLK", "phy_name":"SLICE_24/CLK" }, "pin1": { "log_name":"RST001/Rst_Sync.ff_inst/Q", "phy_name":"SLICE_24/Q1" }, "arrive":4.309, "delay":0.307 }, { "type":"net_delay", "net": { "log_name":"RST001/rst1", "phy_name":"RST001.rst1" }, "arrive":6.788, "delay":2.479 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":6.788, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- --------------- ------------- -------- --------------------- ------ RST001/Rst_Sync.ff_inst/CLK->RST001/Rst_Sync.ff_inst/Q SLICE_R27C83D REG_DEL 0.307 4.309 10 RST001/rst1 NET DELAY 2.479 6.788 10 CNT01/Couti[0].ff_inst/LSR 0.000 6.788 1 Destination Clock Path { "path_begin": { "type":"port", "log_name":"CLK1", "phy_name":"CLK1" }, "path_end": { "type":"pin", "log_name":"CNT01/Couti[0].ff_inst/CLK", "phy_name":"CNT01.SLICE_22/CLK" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":6.667, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"CLK1", "phy_name":"CLK1" }, "arrive":6.667, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"CLK1_pad.bb_inst/B", "phy_name":"CLK1_pad.bb_inst/IOPAD" }, "pin1": { "log_name":"CLK1_pad.bb_inst/O", "phy_name":"CLK1_pad.bb_inst/PADDI" }, "arrive":8.033, "delay":1.366 }, { "type":"net_delay", "net": { "log_name":"RST001/CLK1_c", "phy_name":"CLK1_c" }, "arrive":10.669, "delay":2.636 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":10.669, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- --------------- ------------- -------- --------------------- ------ CONSTRAINT 0.000 6.667 1 CLK1 Top CLOCK LATENCY 0.000 6.667 1 CLK1 NET DELAY 0.000 6.667 1 CLK1_pad.bb_inst/B->CLK1_pad.bb_inst/O SEIO33_CORE_P24 PADI_DEL 1.366 8.033 11 RST001/CLK1_c NET DELAY 2.636 10.669 11 CNT01/Couti[0].ff_inst/CLK 0.000 10.669 1 Uncertainty -(0.000) 10.669 Setup time -(0.205) 10.464 ---------------------------------------- --------------- ------------- -------- --------------------- ------ Required Time 10.464 Arrival Time -(6.788) ---------------------------------------- --------------- ------------- -------- --------------------- ------ Path Slack (Passed) 3.676 ++++ Path 4 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : RST001/Rst_Sync.ff_inst/Q (SLICE_R27C83D) Path End : CNT01/Couti[15].ff_inst/LSR (SLICE_R14C14A) Source Clock : CLK1 (R) Destination Clock: CLK1 (R) Logic Level : 1 Delay Ratio : 89.0% (route), 11.0% (logic) Clock Skew : 0.000 ns Setup Constraint : 6.667 ns Path Slack : 3.676 ns (Passed) Source Clock Path { "path_begin": { "type":"port", "log_name":"CLK1", "phy_name":"CLK1" }, "path_end": { "type":"pin", "log_name":"RST001/Rst_Sync1_reg.ff_inst/CLK", "phy_name":"SLICE_24/CLK" }, "path_sections":[ { "type":"net_delay", "net": { "log_name":"CLK1", "phy_name":"CLK1" }, "arrive":0.000, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"CLK1_pad.bb_inst/B", "phy_name":"CLK1_pad.bb_inst/IOPAD" }, "pin1": { "log_name":"CLK1_pad.bb_inst/O", "phy_name":"CLK1_pad.bb_inst/PADDI" }, "arrive":1.366, "delay":1.366 }, { "type":"net_delay", "net": { "log_name":"RST001/CLK1_c", "phy_name":"CLK1_c" }, "arrive":4.002, "delay":2.636 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":4.002, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- --------------- ------------- -------- --------------------- ------ CLK1 Top CLOCK LATENCY 0.000 0.000 1 CLK1 NET DELAY 0.000 0.000 1 CLK1_pad.bb_inst/B->CLK1_pad.bb_inst/O SEIO33_CORE_P24 PADI_DEL 1.366 1.366 11 RST001/CLK1_c NET DELAY 2.636 4.002 11 {RST001/Rst_Sync1_reg.ff_inst/CLK RST001/Rst_Sync.ff_inst/CLK} 0.000 4.002 1 Data Path { "path_begin": { "type":"pin", "log_name":"RST001/Rst_Sync.ff_inst/Q", "phy_name":"SLICE_24/Q1" }, "path_end": { "type":"pin", "log_name":"CNT01/Couti[15].ff_inst/LSR", "phy_name":"CNT01.SLICE_0/LSR" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"RST001/Rst_Sync.ff_inst/CLK", "phy_name":"SLICE_24/CLK" }, "pin1": { "log_name":"RST001/Rst_Sync.ff_inst/Q", "phy_name":"SLICE_24/Q1" }, "arrive":4.309, "delay":0.307 }, { "type":"net_delay", "net": { "log_name":"RST001/rst1", "phy_name":"RST001.rst1" }, "arrive":6.788, "delay":2.479 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":6.788, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- --------------- ------------- -------- --------------------- ------ RST001/Rst_Sync.ff_inst/CLK->RST001/Rst_Sync.ff_inst/Q SLICE_R27C83D REG_DEL 0.307 4.309 10 RST001/rst1 NET DELAY 2.479 6.788 10 CNT01/Couti[15].ff_inst/LSR 0.000 6.788 1 Destination Clock Path { "path_begin": { "type":"port", "log_name":"CLK1", "phy_name":"CLK1" }, "path_end": { "type":"pin", "log_name":"CNT01/Couti[15].ff_inst/CLK", "phy_name":"CNT01.SLICE_0/CLK" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":6.667, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"CLK1", "phy_name":"CLK1" }, "arrive":6.667, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"CLK1_pad.bb_inst/B", "phy_name":"CLK1_pad.bb_inst/IOPAD" }, "pin1": { "log_name":"CLK1_pad.bb_inst/O", "phy_name":"CLK1_pad.bb_inst/PADDI" }, "arrive":8.033, "delay":1.366 }, { "type":"net_delay", "net": { "log_name":"RST001/CLK1_c", "phy_name":"CLK1_c" }, "arrive":10.669, "delay":2.636 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":10.669, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- --------------- ------------- -------- --------------------- ------ CONSTRAINT 0.000 6.667 1 CLK1 Top CLOCK LATENCY 0.000 6.667 1 CLK1 NET DELAY 0.000 6.667 1 CLK1_pad.bb_inst/B->CLK1_pad.bb_inst/O SEIO33_CORE_P24 PADI_DEL 1.366 8.033 11 RST001/CLK1_c NET DELAY 2.636 10.669 11 CNT01/Couti[15].ff_inst/CLK 0.000 10.669 1 Uncertainty -(0.000) 10.669 Setup time -(0.205) 10.464 ---------------------------------------- --------------- ------------- -------- --------------------- ------ Required Time 10.464 Arrival Time -(6.788) ---------------------------------------- --------------- ------------- -------- --------------------- ------ Path Slack (Passed) 3.676 ++++ Path 5 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : RST001/Rst_Sync.ff_inst/Q (SLICE_R27C83D) Path End : {CNT01/Couti_reg[3].ff_inst/LSR CNT01/Couti_reg[4].ff_inst/LSR} (SLICE_R14C12C) Source Clock : CLK1 (R) Destination Clock: CLK1 (R) Logic Level : 1 Delay Ratio : 88.5% (route), 11.5% (logic) Clock Skew : 0.000 ns Setup Constraint : 6.667 ns Path Slack : 3.801 ns (Passed) Source Clock Path { "path_begin": { "type":"port", "log_name":"CLK1", "phy_name":"CLK1" }, "path_end": { "type":"pin", "log_name":"RST001/Rst_Sync1_reg.ff_inst/CLK", "phy_name":"SLICE_24/CLK" }, "path_sections":[ { "type":"net_delay", "net": { "log_name":"CLK1", "phy_name":"CLK1" }, "arrive":0.000, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"CLK1_pad.bb_inst/B", "phy_name":"CLK1_pad.bb_inst/IOPAD" }, "pin1": { "log_name":"CLK1_pad.bb_inst/O", "phy_name":"CLK1_pad.bb_inst/PADDI" }, "arrive":1.366, "delay":1.366 }, { "type":"net_delay", "net": { "log_name":"RST001/CLK1_c", "phy_name":"CLK1_c" }, "arrive":4.002, "delay":2.636 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":4.002, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- --------------- ------------- -------- --------------------- ------ CLK1 Top CLOCK LATENCY 0.000 0.000 1 CLK1 NET DELAY 0.000 0.000 1 CLK1_pad.bb_inst/B->CLK1_pad.bb_inst/O SEIO33_CORE_P24 PADI_DEL 1.366 1.366 11 RST001/CLK1_c NET DELAY 2.636 4.002 11 {RST001/Rst_Sync1_reg.ff_inst/CLK RST001/Rst_Sync.ff_inst/CLK} 0.000 4.002 1 Data Path { "path_begin": { "type":"pin", "log_name":"RST001/Rst_Sync.ff_inst/Q", "phy_name":"SLICE_24/Q1" }, "path_end": { "type":"pin", "log_name":"{CNT01/Couti_reg[3].ff_inst/LSR CNT01/Couti_reg[4].ff_inst/LSR}", "phy_name":"CNT01.SLICE_6/LSR" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"RST001/Rst_Sync.ff_inst/CLK", "phy_name":"SLICE_24/CLK" }, "pin1": { "log_name":"RST001/Rst_Sync.ff_inst/Q", "phy_name":"SLICE_24/Q1" }, "arrive":4.309, "delay":0.307 }, { "type":"net_delay", "net": { "log_name":"RST001/rst1", "phy_name":"RST001.rst1" }, "arrive":6.663, "delay":2.354 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":6.663, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- --------------- ------------- -------- --------------------- ------ RST001/Rst_Sync.ff_inst/CLK->RST001/Rst_Sync.ff_inst/Q SLICE_R27C83D REG_DEL 0.307 4.309 10 RST001/rst1 NET DELAY 2.354 6.663 10 {CNT01/Couti_reg[3].ff_inst/LSR CNT01/Couti_reg[4].ff_inst/LSR} 0.000 6.663 1 Destination Clock Path { "path_begin": { "type":"port", "log_name":"CLK1", "phy_name":"CLK1" }, "path_end": { "type":"pin", "log_name":"CNT01/Couti_reg[3].ff_inst/CLK", "phy_name":"CNT01.SLICE_6/CLK" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":6.667, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"CLK1", "phy_name":"CLK1" }, "arrive":6.667, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"CLK1_pad.bb_inst/B", "phy_name":"CLK1_pad.bb_inst/IOPAD" }, "pin1": { "log_name":"CLK1_pad.bb_inst/O", "phy_name":"CLK1_pad.bb_inst/PADDI" }, "arrive":8.033, "delay":1.366 }, { "type":"net_delay", "net": { "log_name":"RST001/CLK1_c", "phy_name":"CLK1_c" }, "arrive":10.669, "delay":2.636 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":10.669, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- --------------- ------------- -------- --------------------- ------ CONSTRAINT 0.000 6.667 1 CLK1 Top CLOCK LATENCY 0.000 6.667 1 CLK1 NET DELAY 0.000 6.667 1 CLK1_pad.bb_inst/B->CLK1_pad.bb_inst/O SEIO33_CORE_P24 PADI_DEL 1.366 8.033 11 RST001/CLK1_c NET DELAY 2.636 10.669 11 {CNT01/Couti_reg[3].ff_inst/CLK CNT01/Couti_reg[4].ff_inst/CLK} 0.000 10.669 1 Uncertainty -(0.000) 10.669 Setup time -(0.205) 10.464 ---------------------------------------- --------------- ------------- -------- --------------------- ------ Required Time 10.464 Arrival Time -(6.663) ---------------------------------------- --------------- ------------- -------- --------------------- ------ Path Slack (Passed) 3.801 ++++ Path 6 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : RST001/Rst_Sync.ff_inst/Q (SLICE_R27C83D) Path End : {CNT01/Couti_reg[5].ff_inst/LSR CNT01/Couti_reg[6].ff_inst/LSR} (SLICE_R14C12D) Source Clock : CLK1 (R) Destination Clock: CLK1 (R) Logic Level : 1 Delay Ratio : 88.5% (route), 11.5% (logic) Clock Skew : 0.000 ns Setup Constraint : 6.667 ns Path Slack : 3.801 ns (Passed) Source Clock Path { "path_begin": { "type":"port", "log_name":"CLK1", "phy_name":"CLK1" }, "path_end": { "type":"pin", "log_name":"RST001/Rst_Sync1_reg.ff_inst/CLK", "phy_name":"SLICE_24/CLK" }, "path_sections":[ { "type":"net_delay", "net": { "log_name":"CLK1", "phy_name":"CLK1" }, "arrive":0.000, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"CLK1_pad.bb_inst/B", "phy_name":"CLK1_pad.bb_inst/IOPAD" }, "pin1": { "log_name":"CLK1_pad.bb_inst/O", "phy_name":"CLK1_pad.bb_inst/PADDI" }, "arrive":1.366, "delay":1.366 }, { "type":"net_delay", "net": { "log_name":"RST001/CLK1_c", "phy_name":"CLK1_c" }, "arrive":4.002, "delay":2.636 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":4.002, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- --------------- ------------- -------- --------------------- ------ CLK1 Top CLOCK LATENCY 0.000 0.000 1 CLK1 NET DELAY 0.000 0.000 1 CLK1_pad.bb_inst/B->CLK1_pad.bb_inst/O SEIO33_CORE_P24 PADI_DEL 1.366 1.366 11 RST001/CLK1_c NET DELAY 2.636 4.002 11 {RST001/Rst_Sync1_reg.ff_inst/CLK RST001/Rst_Sync.ff_inst/CLK} 0.000 4.002 1 Data Path { "path_begin": { "type":"pin", "log_name":"RST001/Rst_Sync.ff_inst/Q", "phy_name":"SLICE_24/Q1" }, "path_end": { "type":"pin", "log_name":"{CNT01/Couti_reg[5].ff_inst/LSR CNT01/Couti_reg[6].ff_inst/LSR}", "phy_name":"CNT01.SLICE_5/LSR" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"RST001/Rst_Sync.ff_inst/CLK", "phy_name":"SLICE_24/CLK" }, "pin1": { "log_name":"RST001/Rst_Sync.ff_inst/Q", "phy_name":"SLICE_24/Q1" }, "arrive":4.309, "delay":0.307 }, { "type":"net_delay", "net": { "log_name":"RST001/rst1", "phy_name":"RST001.rst1" }, "arrive":6.663, "delay":2.354 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":6.663, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- --------------- ------------- -------- --------------------- ------ RST001/Rst_Sync.ff_inst/CLK->RST001/Rst_Sync.ff_inst/Q SLICE_R27C83D REG_DEL 0.307 4.309 10 RST001/rst1 NET DELAY 2.354 6.663 10 {CNT01/Couti_reg[5].ff_inst/LSR CNT01/Couti_reg[6].ff_inst/LSR} 0.000 6.663 1 Destination Clock Path { "path_begin": { "type":"port", "log_name":"CLK1", "phy_name":"CLK1" }, "path_end": { "type":"pin", "log_name":"CNT01/Couti_reg[5].ff_inst/CLK", "phy_name":"CNT01.SLICE_5/CLK" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":6.667, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"CLK1", "phy_name":"CLK1" }, "arrive":6.667, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"CLK1_pad.bb_inst/B", "phy_name":"CLK1_pad.bb_inst/IOPAD" }, "pin1": { "log_name":"CLK1_pad.bb_inst/O", "phy_name":"CLK1_pad.bb_inst/PADDI" }, "arrive":8.033, "delay":1.366 }, { "type":"net_delay", "net": { "log_name":"RST001/CLK1_c", "phy_name":"CLK1_c" }, "arrive":10.669, "delay":2.636 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":10.669, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- --------------- ------------- -------- --------------------- ------ CONSTRAINT 0.000 6.667 1 CLK1 Top CLOCK LATENCY 0.000 6.667 1 CLK1 NET DELAY 0.000 6.667 1 CLK1_pad.bb_inst/B->CLK1_pad.bb_inst/O SEIO33_CORE_P24 PADI_DEL 1.366 8.033 11 RST001/CLK1_c NET DELAY 2.636 10.669 11 {CNT01/Couti_reg[5].ff_inst/CLK CNT01/Couti_reg[6].ff_inst/CLK} 0.000 10.669 1 Uncertainty -(0.000) 10.669 Setup time -(0.205) 10.464 ---------------------------------------- --------------- ------------- -------- --------------------- ------ Required Time 10.464 Arrival Time -(6.663) ---------------------------------------- --------------- ------------- -------- --------------------- ------ Path Slack (Passed) 3.801 ++++ Path 7 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : RST001/Rst_Sync.ff_inst/Q (SLICE_R27C83D) Path End : {CNT01/Couti_reg[7].ff_inst/LSR CNT01/Couti_reg[8].ff_inst/LSR} (SLICE_R14C13A) Source Clock : CLK1 (R) Destination Clock: CLK1 (R) Logic Level : 1 Delay Ratio : 88.5% (route), 11.5% (logic) Clock Skew : 0.000 ns Setup Constraint : 6.667 ns Path Slack : 3.801 ns (Passed) Source Clock Path { "path_begin": { "type":"port", "log_name":"CLK1", "phy_name":"CLK1" }, "path_end": { "type":"pin", "log_name":"RST001/Rst_Sync1_reg.ff_inst/CLK", "phy_name":"SLICE_24/CLK" }, "path_sections":[ { "type":"net_delay", "net": { "log_name":"CLK1", "phy_name":"CLK1" }, "arrive":0.000, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"CLK1_pad.bb_inst/B", "phy_name":"CLK1_pad.bb_inst/IOPAD" }, "pin1": { "log_name":"CLK1_pad.bb_inst/O", "phy_name":"CLK1_pad.bb_inst/PADDI" }, "arrive":1.366, "delay":1.366 }, { "type":"net_delay", "net": { "log_name":"RST001/CLK1_c", "phy_name":"CLK1_c" }, "arrive":4.002, "delay":2.636 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":4.002, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- --------------- ------------- -------- --------------------- ------ CLK1 Top CLOCK LATENCY 0.000 0.000 1 CLK1 NET DELAY 0.000 0.000 1 CLK1_pad.bb_inst/B->CLK1_pad.bb_inst/O SEIO33_CORE_P24 PADI_DEL 1.366 1.366 11 RST001/CLK1_c NET DELAY 2.636 4.002 11 {RST001/Rst_Sync1_reg.ff_inst/CLK RST001/Rst_Sync.ff_inst/CLK} 0.000 4.002 1 Data Path { "path_begin": { "type":"pin", "log_name":"RST001/Rst_Sync.ff_inst/Q", "phy_name":"SLICE_24/Q1" }, "path_end": { "type":"pin", "log_name":"{CNT01/Couti_reg[7].ff_inst/LSR CNT01/Couti_reg[8].ff_inst/LSR}", "phy_name":"CNT01.SLICE_4/LSR" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"RST001/Rst_Sync.ff_inst/CLK", "phy_name":"SLICE_24/CLK" }, "pin1": { "log_name":"RST001/Rst_Sync.ff_inst/Q", "phy_name":"SLICE_24/Q1" }, "arrive":4.309, "delay":0.307 }, { "type":"net_delay", "net": { "log_name":"RST001/rst1", "phy_name":"RST001.rst1" }, "arrive":6.663, "delay":2.354 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":6.663, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- --------------- ------------- -------- --------------------- ------ RST001/Rst_Sync.ff_inst/CLK->RST001/Rst_Sync.ff_inst/Q SLICE_R27C83D REG_DEL 0.307 4.309 10 RST001/rst1 NET DELAY 2.354 6.663 10 {CNT01/Couti_reg[7].ff_inst/LSR CNT01/Couti_reg[8].ff_inst/LSR} 0.000 6.663 1 Destination Clock Path { "path_begin": { "type":"port", "log_name":"CLK1", "phy_name":"CLK1" }, "path_end": { "type":"pin", "log_name":"CNT01/Couti_reg[7].ff_inst/CLK", "phy_name":"CNT01.SLICE_4/CLK" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":6.667, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"CLK1", "phy_name":"CLK1" }, "arrive":6.667, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"CLK1_pad.bb_inst/B", "phy_name":"CLK1_pad.bb_inst/IOPAD" }, "pin1": { "log_name":"CLK1_pad.bb_inst/O", "phy_name":"CLK1_pad.bb_inst/PADDI" }, "arrive":8.033, "delay":1.366 }, { "type":"net_delay", "net": { "log_name":"RST001/CLK1_c", "phy_name":"CLK1_c" }, "arrive":10.669, "delay":2.636 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":10.669, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- --------------- ------------- -------- --------------------- ------ CONSTRAINT 0.000 6.667 1 CLK1 Top CLOCK LATENCY 0.000 6.667 1 CLK1 NET DELAY 0.000 6.667 1 CLK1_pad.bb_inst/B->CLK1_pad.bb_inst/O SEIO33_CORE_P24 PADI_DEL 1.366 8.033 11 RST001/CLK1_c NET DELAY 2.636 10.669 11 {CNT01/Couti_reg[7].ff_inst/CLK CNT01/Couti_reg[8].ff_inst/CLK} 0.000 10.669 1 Uncertainty -(0.000) 10.669 Setup time -(0.205) 10.464 ---------------------------------------- --------------- ------------- -------- --------------------- ------ Required Time 10.464 Arrival Time -(6.663) ---------------------------------------- --------------- ------------- -------- --------------------- ------ Path Slack (Passed) 3.801 ++++ Path 8 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : RST001/Rst_Sync.ff_inst/Q (SLICE_R27C83D) Path End : {CNT01/Couti_reg[9].ff_inst/LSR CNT01/Couti_reg[10].ff_inst/LSR} (SLICE_R14C13B) Source Clock : CLK1 (R) Destination Clock: CLK1 (R) Logic Level : 1 Delay Ratio : 88.5% (route), 11.5% (logic) Clock Skew : 0.000 ns Setup Constraint : 6.667 ns Path Slack : 3.801 ns (Passed) Source Clock Path { "path_begin": { "type":"port", "log_name":"CLK1", "phy_name":"CLK1" }, "path_end": { "type":"pin", "log_name":"RST001/Rst_Sync1_reg.ff_inst/CLK", "phy_name":"SLICE_24/CLK" }, "path_sections":[ { "type":"net_delay", "net": { "log_name":"CLK1", "phy_name":"CLK1" }, "arrive":0.000, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"CLK1_pad.bb_inst/B", "phy_name":"CLK1_pad.bb_inst/IOPAD" }, "pin1": { "log_name":"CLK1_pad.bb_inst/O", "phy_name":"CLK1_pad.bb_inst/PADDI" }, "arrive":1.366, "delay":1.366 }, { "type":"net_delay", "net": { "log_name":"RST001/CLK1_c", "phy_name":"CLK1_c" }, "arrive":4.002, "delay":2.636 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":4.002, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- --------------- ------------- -------- --------------------- ------ CLK1 Top CLOCK LATENCY 0.000 0.000 1 CLK1 NET DELAY 0.000 0.000 1 CLK1_pad.bb_inst/B->CLK1_pad.bb_inst/O SEIO33_CORE_P24 PADI_DEL 1.366 1.366 11 RST001/CLK1_c NET DELAY 2.636 4.002 11 {RST001/Rst_Sync1_reg.ff_inst/CLK RST001/Rst_Sync.ff_inst/CLK} 0.000 4.002 1 Data Path { "path_begin": { "type":"pin", "log_name":"RST001/Rst_Sync.ff_inst/Q", "phy_name":"SLICE_24/Q1" }, "path_end": { "type":"pin", "log_name":"{CNT01/Couti_reg[9].ff_inst/LSR CNT01/Couti_reg[10].ff_inst/LSR}", "phy_name":"CNT01.SLICE_3/LSR" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"RST001/Rst_Sync.ff_inst/CLK", "phy_name":"SLICE_24/CLK" }, "pin1": { "log_name":"RST001/Rst_Sync.ff_inst/Q", "phy_name":"SLICE_24/Q1" }, "arrive":4.309, "delay":0.307 }, { "type":"net_delay", "net": { "log_name":"RST001/rst1", "phy_name":"RST001.rst1" }, "arrive":6.663, "delay":2.354 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":6.663, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- --------------- ------------- -------- --------------------- ------ RST001/Rst_Sync.ff_inst/CLK->RST001/Rst_Sync.ff_inst/Q SLICE_R27C83D REG_DEL 0.307 4.309 10 RST001/rst1 NET DELAY 2.354 6.663 10 {CNT01/Couti_reg[9].ff_inst/LSR CNT01/Couti_reg[10].ff_inst/LSR} 0.000 6.663 1 Destination Clock Path { "path_begin": { "type":"port", "log_name":"CLK1", "phy_name":"CLK1" }, "path_end": { "type":"pin", "log_name":"CNT01/Couti_reg[9].ff_inst/CLK", "phy_name":"CNT01.SLICE_3/CLK" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":6.667, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"CLK1", "phy_name":"CLK1" }, "arrive":6.667, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"CLK1_pad.bb_inst/B", "phy_name":"CLK1_pad.bb_inst/IOPAD" }, "pin1": { "log_name":"CLK1_pad.bb_inst/O", "phy_name":"CLK1_pad.bb_inst/PADDI" }, "arrive":8.033, "delay":1.366 }, { "type":"net_delay", "net": { "log_name":"RST001/CLK1_c", "phy_name":"CLK1_c" }, "arrive":10.669, "delay":2.636 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":10.669, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- --------------- ------------- -------- --------------------- ------ CONSTRAINT 0.000 6.667 1 CLK1 Top CLOCK LATENCY 0.000 6.667 1 CLK1 NET DELAY 0.000 6.667 1 CLK1_pad.bb_inst/B->CLK1_pad.bb_inst/O SEIO33_CORE_P24 PADI_DEL 1.366 8.033 11 RST001/CLK1_c NET DELAY 2.636 10.669 11 {CNT01/Couti_reg[9].ff_inst/CLK CNT01/Couti_reg[10].ff_inst/CLK} 0.000 10.669 1 Uncertainty -(0.000) 10.669 Setup time -(0.205) 10.464 ---------------------------------------- --------------- ------------- -------- --------------------- ------ Required Time 10.464 Arrival Time -(6.663) ---------------------------------------- --------------- ------------- -------- --------------------- ------ Path Slack (Passed) 3.801 ++++ Path 9 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : RST001/Rst_Sync.ff_inst/Q (SLICE_R27C83D) Path End : {CNT01/Couti_reg[11].ff_inst/LSR CNT01/Couti_reg[12].ff_inst/LSR} (SLICE_R14C13C) Source Clock : CLK1 (R) Destination Clock: CLK1 (R) Logic Level : 1 Delay Ratio : 88.5% (route), 11.5% (logic) Clock Skew : 0.000 ns Setup Constraint : 6.667 ns Path Slack : 3.801 ns (Passed) Source Clock Path { "path_begin": { "type":"port", "log_name":"CLK1", "phy_name":"CLK1" }, "path_end": { "type":"pin", "log_name":"RST001/Rst_Sync1_reg.ff_inst/CLK", "phy_name":"SLICE_24/CLK" }, "path_sections":[ { "type":"net_delay", "net": { "log_name":"CLK1", "phy_name":"CLK1" }, "arrive":0.000, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"CLK1_pad.bb_inst/B", "phy_name":"CLK1_pad.bb_inst/IOPAD" }, "pin1": { "log_name":"CLK1_pad.bb_inst/O", "phy_name":"CLK1_pad.bb_inst/PADDI" }, "arrive":1.366, "delay":1.366 }, { "type":"net_delay", "net": { "log_name":"RST001/CLK1_c", "phy_name":"CLK1_c" }, "arrive":4.002, "delay":2.636 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":4.002, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- --------------- ------------- -------- --------------------- ------ CLK1 Top CLOCK LATENCY 0.000 0.000 1 CLK1 NET DELAY 0.000 0.000 1 CLK1_pad.bb_inst/B->CLK1_pad.bb_inst/O SEIO33_CORE_P24 PADI_DEL 1.366 1.366 11 RST001/CLK1_c NET DELAY 2.636 4.002 11 {RST001/Rst_Sync1_reg.ff_inst/CLK RST001/Rst_Sync.ff_inst/CLK} 0.000 4.002 1 Data Path { "path_begin": { "type":"pin", "log_name":"RST001/Rst_Sync.ff_inst/Q", "phy_name":"SLICE_24/Q1" }, "path_end": { "type":"pin", "log_name":"{CNT01/Couti_reg[11].ff_inst/LSR CNT01/Couti_reg[12].ff_inst/LSR}", "phy_name":"CNT01.SLICE_2/LSR" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"RST001/Rst_Sync.ff_inst/CLK", "phy_name":"SLICE_24/CLK" }, "pin1": { "log_name":"RST001/Rst_Sync.ff_inst/Q", "phy_name":"SLICE_24/Q1" }, "arrive":4.309, "delay":0.307 }, { "type":"net_delay", "net": { "log_name":"RST001/rst1", "phy_name":"RST001.rst1" }, "arrive":6.663, "delay":2.354 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":6.663, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- --------------- ------------- -------- --------------------- ------ RST001/Rst_Sync.ff_inst/CLK->RST001/Rst_Sync.ff_inst/Q SLICE_R27C83D REG_DEL 0.307 4.309 10 RST001/rst1 NET DELAY 2.354 6.663 10 {CNT01/Couti_reg[11].ff_inst/LSR CNT01/Couti_reg[12].ff_inst/LSR} 0.000 6.663 1 Destination Clock Path { "path_begin": { "type":"port", "log_name":"CLK1", "phy_name":"CLK1" }, "path_end": { "type":"pin", "log_name":"CNT01/Couti_reg[11].ff_inst/CLK", "phy_name":"CNT01.SLICE_2/CLK" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":6.667, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"CLK1", "phy_name":"CLK1" }, "arrive":6.667, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"CLK1_pad.bb_inst/B", "phy_name":"CLK1_pad.bb_inst/IOPAD" }, "pin1": { "log_name":"CLK1_pad.bb_inst/O", "phy_name":"CLK1_pad.bb_inst/PADDI" }, "arrive":8.033, "delay":1.366 }, { "type":"net_delay", "net": { "log_name":"RST001/CLK1_c", "phy_name":"CLK1_c" }, "arrive":10.669, "delay":2.636 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":10.669, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- --------------- ------------- -------- --------------------- ------ CONSTRAINT 0.000 6.667 1 CLK1 Top CLOCK LATENCY 0.000 6.667 1 CLK1 NET DELAY 0.000 6.667 1 CLK1_pad.bb_inst/B->CLK1_pad.bb_inst/O SEIO33_CORE_P24 PADI_DEL 1.366 8.033 11 RST001/CLK1_c NET DELAY 2.636 10.669 11 {CNT01/Couti_reg[11].ff_inst/CLK CNT01/Couti_reg[12].ff_inst/CLK} 0.000 10.669 1 Uncertainty -(0.000) 10.669 Setup time -(0.205) 10.464 ---------------------------------------- --------------- ------------- -------- --------------------- ------ Required Time 10.464 Arrival Time -(6.663) ---------------------------------------- --------------- ------------- -------- --------------------- ------ Path Slack (Passed) 3.801 ++++ Path 10 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : RST001/Rst_Sync.ff_inst/Q (SLICE_R27C83D) Path End : {CNT01/Couti_reg[13].ff_inst/LSR CNT01/Couti_reg[14].ff_inst/LSR} (SLICE_R14C13D) Source Clock : CLK1 (R) Destination Clock: CLK1 (R) Logic Level : 1 Delay Ratio : 88.5% (route), 11.5% (logic) Clock Skew : 0.000 ns Setup Constraint : 6.667 ns Path Slack : 3.801 ns (Passed) Source Clock Path { "path_begin": { "type":"port", "log_name":"CLK1", "phy_name":"CLK1" }, "path_end": { "type":"pin", "log_name":"RST001/Rst_Sync1_reg.ff_inst/CLK", "phy_name":"SLICE_24/CLK" }, "path_sections":[ { "type":"net_delay", "net": { "log_name":"CLK1", "phy_name":"CLK1" }, "arrive":0.000, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"CLK1_pad.bb_inst/B", "phy_name":"CLK1_pad.bb_inst/IOPAD" }, "pin1": { "log_name":"CLK1_pad.bb_inst/O", "phy_name":"CLK1_pad.bb_inst/PADDI" }, "arrive":1.366, "delay":1.366 }, { "type":"net_delay", "net": { "log_name":"RST001/CLK1_c", "phy_name":"CLK1_c" }, "arrive":4.002, "delay":2.636 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":4.002, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- --------------- ------------- -------- --------------------- ------ CLK1 Top CLOCK LATENCY 0.000 0.000 1 CLK1 NET DELAY 0.000 0.000 1 CLK1_pad.bb_inst/B->CLK1_pad.bb_inst/O SEIO33_CORE_P24 PADI_DEL 1.366 1.366 11 RST001/CLK1_c NET DELAY 2.636 4.002 11 {RST001/Rst_Sync1_reg.ff_inst/CLK RST001/Rst_Sync.ff_inst/CLK} 0.000 4.002 1 Data Path { "path_begin": { "type":"pin", "log_name":"RST001/Rst_Sync.ff_inst/Q", "phy_name":"SLICE_24/Q1" }, "path_end": { "type":"pin", "log_name":"{CNT01/Couti_reg[13].ff_inst/LSR CNT01/Couti_reg[14].ff_inst/LSR}", "phy_name":"CNT01.SLICE_1/LSR" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"RST001/Rst_Sync.ff_inst/CLK", "phy_name":"SLICE_24/CLK" }, "pin1": { "log_name":"RST001/Rst_Sync.ff_inst/Q", "phy_name":"SLICE_24/Q1" }, "arrive":4.309, "delay":0.307 }, { "type":"net_delay", "net": { "log_name":"RST001/rst1", "phy_name":"RST001.rst1" }, "arrive":6.663, "delay":2.354 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":6.663, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- --------------- ------------- -------- --------------------- ------ RST001/Rst_Sync.ff_inst/CLK->RST001/Rst_Sync.ff_inst/Q SLICE_R27C83D REG_DEL 0.307 4.309 10 RST001/rst1 NET DELAY 2.354 6.663 10 {CNT01/Couti_reg[13].ff_inst/LSR CNT01/Couti_reg[14].ff_inst/LSR} 0.000 6.663 1 Destination Clock Path { "path_begin": { "type":"port", "log_name":"CLK1", "phy_name":"CLK1" }, "path_end": { "type":"pin", "log_name":"CNT01/Couti_reg[13].ff_inst/CLK", "phy_name":"CNT01.SLICE_1/CLK" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":6.667, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"CLK1", "phy_name":"CLK1" }, "arrive":6.667, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"CLK1_pad.bb_inst/B", "phy_name":"CLK1_pad.bb_inst/IOPAD" }, "pin1": { "log_name":"CLK1_pad.bb_inst/O", "phy_name":"CLK1_pad.bb_inst/PADDI" }, "arrive":8.033, "delay":1.366 }, { "type":"net_delay", "net": { "log_name":"RST001/CLK1_c", "phy_name":"CLK1_c" }, "arrive":10.669, "delay":2.636 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":10.669, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- --------------- ------------- -------- --------------------- ------ CONSTRAINT 0.000 6.667 1 CLK1 Top CLOCK LATENCY 0.000 6.667 1 CLK1 NET DELAY 0.000 6.667 1 CLK1_pad.bb_inst/B->CLK1_pad.bb_inst/O SEIO33_CORE_P24 PADI_DEL 1.366 8.033 11 RST001/CLK1_c NET DELAY 2.636 10.669 11 {CNT01/Couti_reg[13].ff_inst/CLK CNT01/Couti_reg[14].ff_inst/CLK} 0.000 10.669 1 Uncertainty -(0.000) 10.669 Setup time -(0.205) 10.464 ---------------------------------------- --------------- ------------- -------- --------------------- ------ Required Time 10.464 Arrival Time -(6.663) ---------------------------------------- --------------- ------------- -------- --------------------- ------ Path Slack (Passed) 3.801 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ End of Detailed Report for timing paths +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ ########################################################## 3 Hold at Speed Grade m Corner at 0 Degrees 3.1 Endpoint slacks ------------------------------------------------------- Listing 10 End Points | Slack ------------------------------------------------------- RST001/Rst_Sync.ff_inst/DF | 0.162 ns RST002/Rst_Sync.ff_inst/DF | 0.162 ns CNT01/Couti[0].ff_inst/DF | 0.241 ns CNT02/Couti[0].ff_inst/DF | 0.241 ns CNT01/Couti_reg[1].ff_inst/DF | 0.247 ns CNT01/Couti_reg[7].ff_inst/DF | 0.247 ns CNT01/Couti_reg[9].ff_inst/DF | 0.247 ns CNT01/Couti[15].ff_inst/DF | 0.247 ns CNT02/Couti_reg[9].ff_inst/DF | 0.247 ns CNT02/Couti[15].ff_inst/DF | 0.247 ns ------------------------------------------------------- | Hold # of endpoints with negative slack: | 0 | ------------------------------------------------------- 3.2 Detailed Report XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX Detail report of critical paths XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Detailed Report for timing paths +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ ++++Path 1 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : RST001/Rst_Sync1_reg.ff_inst/Q (SLICE_R27C83D) Path End : RST001/Rst_Sync.ff_inst/DF (SLICE_R27C83D) Source Clock : CLK1 (R) Destination Clock: CLK1 (R) Logic Level : 1 Delay Ratio : 33.2% (route), 66.8% (logic) Clock Skew : 0.000 ns Hold Constraint : 0.000 ns Path Slack : 0.162 ns (Passed) Source Clock Path { "path_begin": { "type":"port", "log_name":"CLK1", "phy_name":"CLK1" }, "path_end": { "type":"pin", "log_name":"RST001/Rst_Sync1_reg.ff_inst/CLK", "phy_name":"SLICE_24/CLK" }, "path_sections":[ { "type":"net_delay", "net": { "log_name":"CLK1", "phy_name":"CLK1" }, "arrive":0.000, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"CLK1_pad.bb_inst/B", "phy_name":"CLK1_pad.bb_inst/IOPAD" }, "pin1": { "log_name":"CLK1_pad.bb_inst/O", "phy_name":"CLK1_pad.bb_inst/PADDI" }, "arrive":1.000, "delay":1.000 }, { "type":"net_delay", "net": { "log_name":"RST001/CLK1_c", "phy_name":"CLK1_c" }, "arrive":2.858, "delay":1.858 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":2.858, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- --------------- ------------- ----- --------------------- ------ CLK1 Top CLOCK LATENCY 0.000 0.000 1 CLK1 NET DELAY 0.000 0.000 1 CLK1_pad.bb_inst/B->CLK1_pad.bb_inst/O SEIO33_CORE_P24 PADI_DEL 1.000 1.000 11 RST001/CLK1_c NET DELAY 1.858 2.858 11 {RST001/Rst_Sync1_reg.ff_inst/CLK RST001/Rst_Sync.ff_inst/CLK} 0.000 2.858 1 Data Path { "path_begin": { "type":"pin", "log_name":"RST001/Rst_Sync1_reg.ff_inst/Q", "phy_name":"SLICE_24/Q0" }, "path_end": { "type":"pin", "log_name":"RST001/Rst_Sync.ff_inst/DF", "phy_name":"SLICE_24/M1" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"RST001/Rst_Sync1_reg.ff_inst/CLK", "phy_name":"SLICE_24/CLK" }, "pin1": { "log_name":"RST001/Rst_Sync1_reg.ff_inst/Q", "phy_name":"SLICE_24/Q0" }, "arrive":3.031, "delay":0.173 }, { "type":"net_delay", "net": { "log_name":"RST001/Rst_Sync1", "phy_name":"RST001.Rst_Sync1" }, "arrive":3.117, "delay":0.086 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":3.117, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- --------------- ------------- ----- --------------------- ------ RST001/Rst_Sync1_reg.ff_inst/CLK->RST001/Rst_Sync1_reg.ff_inst/Q SLICE_R27C83D REG_DEL 0.173 3.031 1 RST001/Rst_Sync1 NET DELAY 0.086 3.117 1 RST001/Rst_Sync.ff_inst/DF 0.000 3.117 1 Destination Clock Path { "path_begin": { "type":"port", "log_name":"CLK1", "phy_name":"CLK1" }, "path_end": { "type":"pin", "log_name":"RST001/Rst_Sync1_reg.ff_inst/CLK", "phy_name":"SLICE_24/CLK" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":0.000, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"CLK1", "phy_name":"CLK1" }, "arrive":0.000, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"CLK1_pad.bb_inst/B", "phy_name":"CLK1_pad.bb_inst/IOPAD" }, "pin1": { "log_name":"CLK1_pad.bb_inst/O", "phy_name":"CLK1_pad.bb_inst/PADDI" }, "arrive":1.000, "delay":1.000 }, { "type":"net_delay", "net": { "log_name":"RST001/CLK1_c", "phy_name":"CLK1_c" }, "arrive":2.858, "delay":1.858 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":2.858, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- --------------- ------------- ----- --------------------- ------ CONSTRAINT 0.000 0.000 1 CLK1 Top CLOCK LATENCY 0.000 0.000 1 CLK1 NET DELAY 0.000 0.000 1 CLK1_pad.bb_inst/B->CLK1_pad.bb_inst/O SEIO33_CORE_P24 PADI_DEL 1.000 1.000 11 RST001/CLK1_c NET DELAY 1.858 2.858 11 {RST001/Rst_Sync1_reg.ff_inst/CLK RST001/Rst_Sync.ff_inst/CLK} 0.000 2.858 1 Uncertainty 0.000 2.858 Hold time 0.097 2.955 ---------------------------------------- --------------- ------------- ----- --------------------- ------ Required Time -2.955 Arrival Time 3.117 ---------------------------------------- --------------- ------------- ----- --------------------- ------ Path Slack (Passed) 0.162 ++++ Path 2 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : RST002/Rst_Sync1_reg.ff_inst/Q (SLICE_R27C136D) Path End : RST002/Rst_Sync.ff_inst/DF (SLICE_R27C136D) Source Clock : clk2 (R) Destination Clock: clk2 (R) Logic Level : 1 Delay Ratio : 33.2% (route), 66.8% (logic) Clock Skew : 0.000 ns Hold Constraint : 0.000 ns Path Slack : 0.162 ns (Passed) Source Clock Path { "path_begin": { "type":"port", "log_name":"clk2", "phy_name":"clk2" }, "path_end": { "type":"pin", "log_name":"RST002/Rst_Sync1_reg.ff_inst/CLK", "phy_name":"RST002.Rst_Sync1_reg.SLICE_20/CLK" }, "path_sections":[ { "type":"net_delay", "net": { "log_name":"clk2", "phy_name":"clk2" }, "arrive":0.000, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"clk2_pad.bb_inst/B", "phy_name":"clk2_pad.bb_inst/IOPAD" }, "pin1": { "log_name":"clk2_pad.bb_inst/O", "phy_name":"clk2_pad.bb_inst/PADDI" }, "arrive":1.000, "delay":1.000 }, { "type":"net_delay", "net": { "log_name":"RST002/clk2_c", "phy_name":"clk2_c" }, "arrive":2.774, "delay":1.774 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":2.774, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- --------------- ------------- ----- --------------------- ------ clk2 Top CLOCK LATENCY 0.000 0.000 1 clk2 NET DELAY 0.000 0.000 1 clk2_pad.bb_inst/B->clk2_pad.bb_inst/O SEIO33_CORE_P22 PADI_DEL 1.000 1.000 11 RST002/clk2_c NET DELAY 1.774 2.774 11 {RST002/Rst_Sync1_reg.ff_inst/CLK RST002/Rst_Sync.ff_inst/CLK} 0.000 2.774 1 Data Path { "path_begin": { "type":"pin", "log_name":"RST002/Rst_Sync1_reg.ff_inst/Q", "phy_name":"RST002.Rst_Sync1_reg.SLICE_20/Q0" }, "path_end": { "type":"pin", "log_name":"RST002/Rst_Sync.ff_inst/DF", "phy_name":"RST002.Rst_Sync1_reg.SLICE_20/M1" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"RST002/Rst_Sync1_reg.ff_inst/CLK", "phy_name":"RST002.Rst_Sync1_reg.SLICE_20/CLK" }, "pin1": { "log_name":"RST002/Rst_Sync1_reg.ff_inst/Q", "phy_name":"RST002.Rst_Sync1_reg.SLICE_20/Q0" }, "arrive":2.947, "delay":0.173 }, { "type":"net_delay", "net": { "log_name":"RST002/Rst_Sync1", "phy_name":"RST002.Rst_Sync1" }, "arrive":3.033, "delay":0.086 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":3.033, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- --------------- ------------- ----- --------------------- ------ RST002/Rst_Sync1_reg.ff_inst/CLK->RST002/Rst_Sync1_reg.ff_inst/Q SLICE_R27C136D REG_DEL 0.173 2.947 1 RST002/Rst_Sync1 NET DELAY 0.086 3.033 1 RST002/Rst_Sync.ff_inst/DF 0.000 3.033 1 Destination Clock Path { "path_begin": { "type":"port", "log_name":"clk2", "phy_name":"clk2" }, "path_end": { "type":"pin", "log_name":"RST002/Rst_Sync1_reg.ff_inst/CLK", "phy_name":"RST002.Rst_Sync1_reg.SLICE_20/CLK" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":0.000, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"clk2", "phy_name":"clk2" }, "arrive":0.000, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"clk2_pad.bb_inst/B", "phy_name":"clk2_pad.bb_inst/IOPAD" }, "pin1": { "log_name":"clk2_pad.bb_inst/O", "phy_name":"clk2_pad.bb_inst/PADDI" }, "arrive":1.000, "delay":1.000 }, { "type":"net_delay", "net": { "log_name":"RST002/clk2_c", "phy_name":"clk2_c" }, "arrive":2.774, "delay":1.774 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":2.774, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- --------------- ------------- ----- --------------------- ------ CONSTRAINT 0.000 0.000 1 clk2 Top CLOCK LATENCY 0.000 0.000 1 clk2 NET DELAY 0.000 0.000 1 clk2_pad.bb_inst/B->clk2_pad.bb_inst/O SEIO33_CORE_P22 PADI_DEL 1.000 1.000 11 RST002/clk2_c NET DELAY 1.774 2.774 11 {RST002/Rst_Sync1_reg.ff_inst/CLK RST002/Rst_Sync.ff_inst/CLK} 0.000 2.774 1 Uncertainty 0.000 2.774 Hold time 0.097 2.871 ---------------------------------------- --------------- ------------- ----- --------------------- ------ Required Time -2.871 Arrival Time 3.033 ---------------------------------------- --------------- ------------- ----- --------------------- ------ Path Slack (Passed) 0.162 ++++ Path 3 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : CNT01/Couti[0].ff_inst/Q (SLICE_R14C14D) Path End : CNT01/Couti[0].ff_inst/DF (SLICE_R14C14D) Source Clock : CLK1 (R) Destination Clock: CLK1 (R) Logic Level : 2 Delay Ratio : 18.6% (route), 81.4% (logic) Clock Skew : 0.000 ns Hold Constraint : 0.000 ns Path Slack : 0.241 ns (Passed) Source Clock Path { "path_begin": { "type":"port", "log_name":"CLK1", "phy_name":"CLK1" }, "path_end": { "type":"pin", "log_name":"CNT01/Couti[0].ff_inst/CLK", "phy_name":"CNT01.SLICE_22/CLK" }, "path_sections":[ { "type":"net_delay", "net": { "log_name":"CLK1", "phy_name":"CLK1" }, "arrive":0.000, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"CLK1_pad.bb_inst/B", "phy_name":"CLK1_pad.bb_inst/IOPAD" }, "pin1": { "log_name":"CLK1_pad.bb_inst/O", "phy_name":"CLK1_pad.bb_inst/PADDI" }, "arrive":1.000, "delay":1.000 }, { "type":"net_delay", "net": { "log_name":"RST001/CLK1_c", "phy_name":"CLK1_c" }, "arrive":2.858, "delay":1.858 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":2.858, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- --------------- ------------- ----- --------------------- ------ CLK1 Top CLOCK LATENCY 0.000 0.000 1 CLK1 NET DELAY 0.000 0.000 1 CLK1_pad.bb_inst/B->CLK1_pad.bb_inst/O SEIO33_CORE_P24 PADI_DEL 1.000 1.000 11 RST001/CLK1_c NET DELAY 1.858 2.858 11 CNT01/Couti[0].ff_inst/CLK 0.000 2.858 1 Data Path { "path_begin": { "type":"pin", "log_name":"CNT01/Couti[0].ff_inst/Q", "phy_name":"CNT01.SLICE_22/Q0" }, "path_end": { "type":"pin", "log_name":"CNT01/Couti[0].ff_inst/DF", "phy_name":"CNT01.SLICE_22/DI0" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"CNT01/Couti[0].ff_inst/CLK", "phy_name":"CNT01.SLICE_22/CLK" }, "pin1": { "log_name":"CNT01/Couti[0].ff_inst/Q", "phy_name":"CNT01.SLICE_22/Q0" }, "arrive":3.031, "delay":0.173 }, { "type":"net_delay", "net": { "log_name":"CNT01/CNT1_0", "phy_name":"CNT1[0]" }, "arrive":3.097, "delay":0.066 }, { "type":"site_delay", "pin0": { "log_name":"CNT01/Couti_RNO[0]/A", "phy_name":"CNT01.SLICE_22/B0" }, "pin1": { "log_name":"CNT01/Couti_RNO[0]/Z", "phy_name":"CNT01.SLICE_22/F0" }, "arrive":3.213, "delay":0.116 }, { "type":"net_delay", "net": { "log_name":"CNT01/CNT1_i[0]", "phy_name":"CNT01.CNT1_i[0]" }, "arrive":3.213, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":3.213, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- --------------- ------------- ----- --------------------- ------ CNT01/Couti[0].ff_inst/CLK->CNT01/Couti[0].ff_inst/Q SLICE_R14C14D REG_DEL 0.173 3.031 3 CNT01/CNT1_0 NET DELAY 0.066 3.097 3 CNT01/Couti_RNO[0]/A->CNT01/Couti_RNO[0]/Z SLICE_R14C14D CTOF_DEL 0.116 3.213 1 CNT01/CNT1_i[0] NET DELAY 0.000 3.213 1 CNT01/Couti[0].ff_inst/DF 0.000 3.213 1 Destination Clock Path { "path_begin": { "type":"port", "log_name":"CLK1", "phy_name":"CLK1" }, "path_end": { "type":"pin", "log_name":"CNT01/Couti[0].ff_inst/CLK", "phy_name":"CNT01.SLICE_22/CLK" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":0.000, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"CLK1", "phy_name":"CLK1" }, "arrive":0.000, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"CLK1_pad.bb_inst/B", "phy_name":"CLK1_pad.bb_inst/IOPAD" }, "pin1": { "log_name":"CLK1_pad.bb_inst/O", "phy_name":"CLK1_pad.bb_inst/PADDI" }, "arrive":1.000, "delay":1.000 }, { "type":"net_delay", "net": { "log_name":"RST001/CLK1_c", "phy_name":"CLK1_c" }, "arrive":2.858, "delay":1.858 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":2.858, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- --------------- ------------- ----- --------------------- ------ CONSTRAINT 0.000 0.000 1 CLK1 Top CLOCK LATENCY 0.000 0.000 1 CLK1 NET DELAY 0.000 0.000 1 CLK1_pad.bb_inst/B->CLK1_pad.bb_inst/O SEIO33_CORE_P24 PADI_DEL 1.000 1.000 11 RST001/CLK1_c NET DELAY 1.858 2.858 11 CNT01/Couti[0].ff_inst/CLK 0.000 2.858 1 Uncertainty 0.000 2.858 Hold time 0.114 2.972 ---------------------------------------- --------------- ------------- ----- --------------------- ------ Required Time -2.972 Arrival Time 3.213 ---------------------------------------- --------------- ------------- ----- --------------------- ------ Path Slack (Passed) 0.241 ++++ Path 4 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : CNT02/Couti[0].ff_inst/Q (SLICE_R30C83D) Path End : CNT02/Couti[0].ff_inst/DF (SLICE_R30C83D) Source Clock : clk2 (R) Destination Clock: clk2 (R) Logic Level : 2 Delay Ratio : 18.6% (route), 81.4% (logic) Clock Skew : 0.000 ns Hold Constraint : 0.000 ns Path Slack : 0.241 ns (Passed) Source Clock Path { "path_begin": { "type":"port", "log_name":"clk2", "phy_name":"clk2" }, "path_end": { "type":"pin", "log_name":"CNT02/Couti[0].ff_inst/CLK", "phy_name":"CNT02.SLICE_23/CLK" }, "path_sections":[ { "type":"net_delay", "net": { "log_name":"clk2", "phy_name":"clk2" }, "arrive":0.000, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"clk2_pad.bb_inst/B", "phy_name":"clk2_pad.bb_inst/IOPAD" }, "pin1": { "log_name":"clk2_pad.bb_inst/O", "phy_name":"clk2_pad.bb_inst/PADDI" }, "arrive":1.000, "delay":1.000 }, { "type":"net_delay", "net": { "log_name":"RST002/clk2_c", "phy_name":"clk2_c" }, "arrive":2.774, "delay":1.774 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":2.774, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- --------------- ------------- ----- --------------------- ------ clk2 Top CLOCK LATENCY 0.000 0.000 1 clk2 NET DELAY 0.000 0.000 1 clk2_pad.bb_inst/B->clk2_pad.bb_inst/O SEIO33_CORE_P22 PADI_DEL 1.000 1.000 11 RST002/clk2_c NET DELAY 1.774 2.774 11 CNT02/Couti[0].ff_inst/CLK 0.000 2.774 1 Data Path { "path_begin": { "type":"pin", "log_name":"CNT02/Couti[0].ff_inst/Q", "phy_name":"CNT02.SLICE_23/Q0" }, "path_end": { "type":"pin", "log_name":"CNT02/Couti[0].ff_inst/DF", "phy_name":"CNT02.SLICE_23/DI0" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"CNT02/Couti[0].ff_inst/CLK", "phy_name":"CNT02.SLICE_23/CLK" }, "pin1": { "log_name":"CNT02/Couti[0].ff_inst/Q", "phy_name":"CNT02.SLICE_23/Q0" }, "arrive":2.947, "delay":0.173 }, { "type":"net_delay", "net": { "log_name":"CNT02/CNT2_0", "phy_name":"CNT2[0]" }, "arrive":3.013, "delay":0.066 }, { "type":"site_delay", "pin0": { "log_name":"CNT02/Couti_RNO[0]/A", "phy_name":"CNT02.SLICE_23/B0" }, "pin1": { "log_name":"CNT02/Couti_RNO[0]/Z", "phy_name":"CNT02.SLICE_23/F0" }, "arrive":3.129, "delay":0.116 }, { "type":"net_delay", "net": { "log_name":"CNT02/CNT2_i[0]", "phy_name":"CNT02.CNT2_i[0]" }, "arrive":3.129, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":3.129, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- --------------- ------------- ----- --------------------- ------ CNT02/Couti[0].ff_inst/CLK->CNT02/Couti[0].ff_inst/Q SLICE_R30C83D REG_DEL 0.173 2.947 3 CNT02/CNT2_0 NET DELAY 0.066 3.013 3 CNT02/Couti_RNO[0]/A->CNT02/Couti_RNO[0]/Z SLICE_R30C83D CTOF_DEL 0.116 3.129 1 CNT02/CNT2_i[0] NET DELAY 0.000 3.129 1 CNT02/Couti[0].ff_inst/DF 0.000 3.129 1 Destination Clock Path { "path_begin": { "type":"port", "log_name":"clk2", "phy_name":"clk2" }, "path_end": { "type":"pin", "log_name":"CNT02/Couti[0].ff_inst/CLK", "phy_name":"CNT02.SLICE_23/CLK" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":0.000, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"clk2", "phy_name":"clk2" }, "arrive":0.000, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"clk2_pad.bb_inst/B", "phy_name":"clk2_pad.bb_inst/IOPAD" }, "pin1": { "log_name":"clk2_pad.bb_inst/O", "phy_name":"clk2_pad.bb_inst/PADDI" }, "arrive":1.000, "delay":1.000 }, { "type":"net_delay", "net": { "log_name":"RST002/clk2_c", "phy_name":"clk2_c" }, "arrive":2.774, "delay":1.774 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":2.774, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- --------------- ------------- ----- --------------------- ------ CONSTRAINT 0.000 0.000 1 clk2 Top CLOCK LATENCY 0.000 0.000 1 clk2 NET DELAY 0.000 0.000 1 clk2_pad.bb_inst/B->clk2_pad.bb_inst/O SEIO33_CORE_P22 PADI_DEL 1.000 1.000 11 RST002/clk2_c NET DELAY 1.774 2.774 11 CNT02/Couti[0].ff_inst/CLK 0.000 2.774 1 Uncertainty 0.000 2.774 Hold time 0.114 2.888 ---------------------------------------- --------------- ------------- ----- --------------------- ------ Required Time -2.888 Arrival Time 3.129 ---------------------------------------- --------------- ------------- ----- --------------------- ------ Path Slack (Passed) 0.241 ++++ Path 5 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : CNT01/Couti_reg[1].ff_inst/Q (SLICE_R14C12B) Path End : CNT01/Couti_reg[1].ff_inst/DF (SLICE_R14C12B) Source Clock : CLK1 (R) Destination Clock: CLK1 (R) Logic Level : 2 Delay Ratio : 19.9% (route), 80.1% (logic) Clock Skew : 0.000 ns Hold Constraint : 0.000 ns Path Slack : 0.247 ns (Passed) Source Clock Path { "path_begin": { "type":"port", "log_name":"CLK1", "phy_name":"CLK1" }, "path_end": { "type":"pin", "log_name":"CNT01/Couti_reg[1].ff_inst/CLK", "phy_name":"CNT01.SLICE_7/CLK" }, "path_sections":[ { "type":"net_delay", "net": { "log_name":"CLK1", "phy_name":"CLK1" }, "arrive":0.000, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"CLK1_pad.bb_inst/B", "phy_name":"CLK1_pad.bb_inst/IOPAD" }, "pin1": { "log_name":"CLK1_pad.bb_inst/O", "phy_name":"CLK1_pad.bb_inst/PADDI" }, "arrive":1.000, "delay":1.000 }, { "type":"net_delay", "net": { "log_name":"RST001/CLK1_c", "phy_name":"CLK1_c" }, "arrive":2.858, "delay":1.858 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":2.858, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- --------------- ------------- ----- --------------------- ------ CLK1 Top CLOCK LATENCY 0.000 0.000 1 CLK1 NET DELAY 0.000 0.000 1 CLK1_pad.bb_inst/B->CLK1_pad.bb_inst/O SEIO33_CORE_P24 PADI_DEL 1.000 1.000 11 RST001/CLK1_c NET DELAY 1.858 2.858 11 {CNT01/Couti_reg[1].ff_inst/CLK CNT01/Couti_reg[2].ff_inst/CLK} 0.000 2.858 1 Data Path { "path_begin": { "type":"pin", "log_name":"CNT01/Couti_reg[1].ff_inst/Q", "phy_name":"CNT01.SLICE_7/Q0" }, "path_end": { "type":"pin", "log_name":"CNT01/Couti_reg[1].ff_inst/DF", "phy_name":"CNT01.SLICE_7/DI0" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"CNT01/Couti_reg[1].ff_inst/CLK", "phy_name":"CNT01.SLICE_7/CLK" }, "pin1": { "log_name":"CNT01/Couti_reg[1].ff_inst/Q", "phy_name":"CNT01.SLICE_7/Q0" }, "arrive":3.031, "delay":0.173 }, { "type":"net_delay", "net": { "log_name":"CNT01/Couti[1]", "phy_name":"CNT01.Couti[1]" }, "arrive":3.103, "delay":0.072 }, { "type":"site_delay", "pin0": { "log_name":"CNT01/un3_couti_cry_1_0/A0", "phy_name":"CNT01.SLICE_7/A0" }, "pin1": { "log_name":"CNT01/un3_couti_cry_1_0/S0", "phy_name":"CNT01.SLICE_7/F0" }, "arrive":3.219, "delay":0.116 }, { "type":"net_delay", "net": { "log_name":"CNT01/un3_couti[1]", "phy_name":"CNT01.un3_couti[1]" }, "arrive":3.219, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":3.219, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- --------------- ------------- ----- --------------------- ------ CNT01/Couti_reg[1].ff_inst/CLK->CNT01/Couti_reg[1].ff_inst/Q SLICE_R14C12B REG_DEL 0.173 3.031 1 CNT01/Couti[1] NET DELAY 0.072 3.103 1 CNT01/un3_couti_cry_1_0/A0->CNT01/un3_couti_cry_1_0/S0 SLICE_R14C12B CTOF_DEL 0.116 3.219 1 CNT01/un3_couti[1] NET DELAY 0.000 3.219 1 CNT01/Couti_reg[1].ff_inst/DF 0.000 3.219 1 Destination Clock Path { "path_begin": { "type":"port", "log_name":"CLK1", "phy_name":"CLK1" }, "path_end": { "type":"pin", "log_name":"CNT01/Couti_reg[1].ff_inst/CLK", "phy_name":"CNT01.SLICE_7/CLK" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":0.000, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"CLK1", "phy_name":"CLK1" }, "arrive":0.000, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"CLK1_pad.bb_inst/B", "phy_name":"CLK1_pad.bb_inst/IOPAD" }, "pin1": { "log_name":"CLK1_pad.bb_inst/O", "phy_name":"CLK1_pad.bb_inst/PADDI" }, "arrive":1.000, "delay":1.000 }, { "type":"net_delay", "net": { "log_name":"RST001/CLK1_c", "phy_name":"CLK1_c" }, "arrive":2.858, "delay":1.858 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":2.858, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- --------------- ------------- ----- --------------------- ------ CONSTRAINT 0.000 0.000 1 CLK1 Top CLOCK LATENCY 0.000 0.000 1 CLK1 NET DELAY 0.000 0.000 1 CLK1_pad.bb_inst/B->CLK1_pad.bb_inst/O SEIO33_CORE_P24 PADI_DEL 1.000 1.000 11 RST001/CLK1_c NET DELAY 1.858 2.858 11 {CNT01/Couti_reg[1].ff_inst/CLK CNT01/Couti_reg[2].ff_inst/CLK} 0.000 2.858 1 Uncertainty 0.000 2.858 Hold time 0.114 2.972 ---------------------------------------- --------------- ------------- ----- --------------------- ------ Required Time -2.972 Arrival Time 3.219 ---------------------------------------- --------------- ------------- ----- --------------------- ------ Path Slack (Passed) 0.247 ++++ Path 6 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : CNT01/Couti_reg[7].ff_inst/Q (SLICE_R14C13A) Path End : CNT01/Couti_reg[7].ff_inst/DF (SLICE_R14C13A) Source Clock : CLK1 (R) Destination Clock: CLK1 (R) Logic Level : 2 Delay Ratio : 19.9% (route), 80.1% (logic) Clock Skew : 0.000 ns Hold Constraint : 0.000 ns Path Slack : 0.247 ns (Passed) Source Clock Path { "path_begin": { "type":"port", "log_name":"CLK1", "phy_name":"CLK1" }, "path_end": { "type":"pin", "log_name":"CNT01/Couti_reg[7].ff_inst/CLK", "phy_name":"CNT01.SLICE_4/CLK" }, "path_sections":[ { "type":"net_delay", "net": { "log_name":"CLK1", "phy_name":"CLK1" }, "arrive":0.000, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"CLK1_pad.bb_inst/B", "phy_name":"CLK1_pad.bb_inst/IOPAD" }, "pin1": { "log_name":"CLK1_pad.bb_inst/O", "phy_name":"CLK1_pad.bb_inst/PADDI" }, "arrive":1.000, "delay":1.000 }, { "type":"net_delay", "net": { "log_name":"RST001/CLK1_c", "phy_name":"CLK1_c" }, "arrive":2.858, "delay":1.858 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":2.858, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- --------------- ------------- ----- --------------------- ------ CLK1 Top CLOCK LATENCY 0.000 0.000 1 CLK1 NET DELAY 0.000 0.000 1 CLK1_pad.bb_inst/B->CLK1_pad.bb_inst/O SEIO33_CORE_P24 PADI_DEL 1.000 1.000 11 RST001/CLK1_c NET DELAY 1.858 2.858 11 {CNT01/Couti_reg[7].ff_inst/CLK CNT01/Couti_reg[8].ff_inst/CLK} 0.000 2.858 1 Data Path { "path_begin": { "type":"pin", "log_name":"CNT01/Couti_reg[7].ff_inst/Q", "phy_name":"CNT01.SLICE_4/Q0" }, "path_end": { "type":"pin", "log_name":"CNT01/Couti_reg[7].ff_inst/DF", "phy_name":"CNT01.SLICE_4/DI0" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"CNT01/Couti_reg[7].ff_inst/CLK", "phy_name":"CNT01.SLICE_4/CLK" }, "pin1": { "log_name":"CNT01/Couti_reg[7].ff_inst/Q", "phy_name":"CNT01.SLICE_4/Q0" }, "arrive":3.031, "delay":0.173 }, { "type":"net_delay", "net": { "log_name":"CNT01/Couti[7]", "phy_name":"CNT01.Couti[7]" }, "arrive":3.103, "delay":0.072 }, { "type":"site_delay", "pin0": { "log_name":"CNT01/un3_couti_cry_7_0/A0", "phy_name":"CNT01.SLICE_4/A0" }, "pin1": { "log_name":"CNT01/un3_couti_cry_7_0/S0", "phy_name":"CNT01.SLICE_4/F0" }, "arrive":3.219, "delay":0.116 }, { "type":"net_delay", "net": { "log_name":"CNT01/un3_couti[7]", "phy_name":"CNT01.un3_couti[7]" }, "arrive":3.219, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":3.219, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- --------------- ------------- ----- --------------------- ------ CNT01/Couti_reg[7].ff_inst/CLK->CNT01/Couti_reg[7].ff_inst/Q SLICE_R14C13A REG_DEL 0.173 3.031 1 CNT01/Couti[7] NET DELAY 0.072 3.103 1 CNT01/un3_couti_cry_7_0/A0->CNT01/un3_couti_cry_7_0/S0 SLICE_R14C13A CTOF_DEL 0.116 3.219 1 CNT01/un3_couti[7] NET DELAY 0.000 3.219 1 CNT01/Couti_reg[7].ff_inst/DF 0.000 3.219 1 Destination Clock Path { "path_begin": { "type":"port", "log_name":"CLK1", "phy_name":"CLK1" }, "path_end": { "type":"pin", "log_name":"CNT01/Couti_reg[7].ff_inst/CLK", "phy_name":"CNT01.SLICE_4/CLK" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":0.000, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"CLK1", "phy_name":"CLK1" }, "arrive":0.000, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"CLK1_pad.bb_inst/B", "phy_name":"CLK1_pad.bb_inst/IOPAD" }, "pin1": { "log_name":"CLK1_pad.bb_inst/O", "phy_name":"CLK1_pad.bb_inst/PADDI" }, "arrive":1.000, "delay":1.000 }, { "type":"net_delay", "net": { "log_name":"RST001/CLK1_c", "phy_name":"CLK1_c" }, "arrive":2.858, "delay":1.858 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":2.858, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- --------------- ------------- ----- --------------------- ------ CONSTRAINT 0.000 0.000 1 CLK1 Top CLOCK LATENCY 0.000 0.000 1 CLK1 NET DELAY 0.000 0.000 1 CLK1_pad.bb_inst/B->CLK1_pad.bb_inst/O SEIO33_CORE_P24 PADI_DEL 1.000 1.000 11 RST001/CLK1_c NET DELAY 1.858 2.858 11 {CNT01/Couti_reg[7].ff_inst/CLK CNT01/Couti_reg[8].ff_inst/CLK} 0.000 2.858 1 Uncertainty 0.000 2.858 Hold time 0.114 2.972 ---------------------------------------- --------------- ------------- ----- --------------------- ------ Required Time -2.972 Arrival Time 3.219 ---------------------------------------- --------------- ------------- ----- --------------------- ------ Path Slack (Passed) 0.247 ++++ Path 7 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : CNT01/Couti_reg[9].ff_inst/Q (SLICE_R14C13B) Path End : CNT01/Couti_reg[9].ff_inst/DF (SLICE_R14C13B) Source Clock : CLK1 (R) Destination Clock: CLK1 (R) Logic Level : 2 Delay Ratio : 19.9% (route), 80.1% (logic) Clock Skew : 0.000 ns Hold Constraint : 0.000 ns Path Slack : 0.247 ns (Passed) Source Clock Path { "path_begin": { "type":"port", "log_name":"CLK1", "phy_name":"CLK1" }, "path_end": { "type":"pin", "log_name":"CNT01/Couti_reg[9].ff_inst/CLK", "phy_name":"CNT01.SLICE_3/CLK" }, "path_sections":[ { "type":"net_delay", "net": { "log_name":"CLK1", "phy_name":"CLK1" }, "arrive":0.000, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"CLK1_pad.bb_inst/B", "phy_name":"CLK1_pad.bb_inst/IOPAD" }, "pin1": { "log_name":"CLK1_pad.bb_inst/O", "phy_name":"CLK1_pad.bb_inst/PADDI" }, "arrive":1.000, "delay":1.000 }, { "type":"net_delay", "net": { "log_name":"RST001/CLK1_c", "phy_name":"CLK1_c" }, "arrive":2.858, "delay":1.858 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":2.858, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- --------------- ------------- ----- --------------------- ------ CLK1 Top CLOCK LATENCY 0.000 0.000 1 CLK1 NET DELAY 0.000 0.000 1 CLK1_pad.bb_inst/B->CLK1_pad.bb_inst/O SEIO33_CORE_P24 PADI_DEL 1.000 1.000 11 RST001/CLK1_c NET DELAY 1.858 2.858 11 {CNT01/Couti_reg[9].ff_inst/CLK CNT01/Couti_reg[10].ff_inst/CLK} 0.000 2.858 1 Data Path { "path_begin": { "type":"pin", "log_name":"CNT01/Couti_reg[9].ff_inst/Q", "phy_name":"CNT01.SLICE_3/Q0" }, "path_end": { "type":"pin", "log_name":"CNT01/Couti_reg[9].ff_inst/DF", "phy_name":"CNT01.SLICE_3/DI0" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"CNT01/Couti_reg[9].ff_inst/CLK", "phy_name":"CNT01.SLICE_3/CLK" }, "pin1": { "log_name":"CNT01/Couti_reg[9].ff_inst/Q", "phy_name":"CNT01.SLICE_3/Q0" }, "arrive":3.031, "delay":0.173 }, { "type":"net_delay", "net": { "log_name":"CNT01/Couti[9]", "phy_name":"CNT01.Couti[9]" }, "arrive":3.103, "delay":0.072 }, { "type":"site_delay", "pin0": { "log_name":"CNT01/un3_couti_cry_9_0/A0", "phy_name":"CNT01.SLICE_3/A0" }, "pin1": { "log_name":"CNT01/un3_couti_cry_9_0/S0", "phy_name":"CNT01.SLICE_3/F0" }, "arrive":3.219, "delay":0.116 }, { "type":"net_delay", "net": { "log_name":"CNT01/un3_couti[9]", "phy_name":"CNT01.un3_couti[9]" }, "arrive":3.219, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":3.219, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- --------------- ------------- ----- --------------------- ------ CNT01/Couti_reg[9].ff_inst/CLK->CNT01/Couti_reg[9].ff_inst/Q SLICE_R14C13B REG_DEL 0.173 3.031 1 CNT01/Couti[9] NET DELAY 0.072 3.103 1 CNT01/un3_couti_cry_9_0/A0->CNT01/un3_couti_cry_9_0/S0 SLICE_R14C13B CTOF_DEL 0.116 3.219 1 CNT01/un3_couti[9] NET DELAY 0.000 3.219 1 CNT01/Couti_reg[9].ff_inst/DF 0.000 3.219 1 Destination Clock Path { "path_begin": { "type":"port", "log_name":"CLK1", "phy_name":"CLK1" }, "path_end": { "type":"pin", "log_name":"CNT01/Couti_reg[9].ff_inst/CLK", "phy_name":"CNT01.SLICE_3/CLK" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":0.000, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"CLK1", "phy_name":"CLK1" }, "arrive":0.000, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"CLK1_pad.bb_inst/B", "phy_name":"CLK1_pad.bb_inst/IOPAD" }, "pin1": { "log_name":"CLK1_pad.bb_inst/O", "phy_name":"CLK1_pad.bb_inst/PADDI" }, "arrive":1.000, "delay":1.000 }, { "type":"net_delay", "net": { "log_name":"RST001/CLK1_c", "phy_name":"CLK1_c" }, "arrive":2.858, "delay":1.858 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":2.858, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- --------------- ------------- ----- --------------------- ------ CONSTRAINT 0.000 0.000 1 CLK1 Top CLOCK LATENCY 0.000 0.000 1 CLK1 NET DELAY 0.000 0.000 1 CLK1_pad.bb_inst/B->CLK1_pad.bb_inst/O SEIO33_CORE_P24 PADI_DEL 1.000 1.000 11 RST001/CLK1_c NET DELAY 1.858 2.858 11 {CNT01/Couti_reg[9].ff_inst/CLK CNT01/Couti_reg[10].ff_inst/CLK} 0.000 2.858 1 Uncertainty 0.000 2.858 Hold time 0.114 2.972 ---------------------------------------- --------------- ------------- ----- --------------------- ------ Required Time -2.972 Arrival Time 3.219 ---------------------------------------- --------------- ------------- ----- --------------------- ------ Path Slack (Passed) 0.247 ++++ Path 8 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : CNT01/Couti[15].ff_inst/Q (SLICE_R14C14A) Path End : CNT01/Couti[15].ff_inst/DF (SLICE_R14C14A) Source Clock : CLK1 (R) Destination Clock: CLK1 (R) Logic Level : 2 Delay Ratio : 19.9% (route), 80.1% (logic) Clock Skew : 0.000 ns Hold Constraint : 0.000 ns Path Slack : 0.247 ns (Passed) Source Clock Path { "path_begin": { "type":"port", "log_name":"CLK1", "phy_name":"CLK1" }, "path_end": { "type":"pin", "log_name":"CNT01/Couti[15].ff_inst/CLK", "phy_name":"CNT01.SLICE_0/CLK" }, "path_sections":[ { "type":"net_delay", "net": { "log_name":"CLK1", "phy_name":"CLK1" }, "arrive":0.000, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"CLK1_pad.bb_inst/B", "phy_name":"CLK1_pad.bb_inst/IOPAD" }, "pin1": { "log_name":"CLK1_pad.bb_inst/O", "phy_name":"CLK1_pad.bb_inst/PADDI" }, "arrive":1.000, "delay":1.000 }, { "type":"net_delay", "net": { "log_name":"RST001/CLK1_c", "phy_name":"CLK1_c" }, "arrive":2.858, "delay":1.858 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":2.858, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- --------------- ------------- ----- --------------------- ------ CLK1 Top CLOCK LATENCY 0.000 0.000 1 CLK1 NET DELAY 0.000 0.000 1 CLK1_pad.bb_inst/B->CLK1_pad.bb_inst/O SEIO33_CORE_P24 PADI_DEL 1.000 1.000 11 RST001/CLK1_c NET DELAY 1.858 2.858 11 CNT01/Couti[15].ff_inst/CLK 0.000 2.858 1 Data Path { "path_begin": { "type":"pin", "log_name":"CNT01/Couti[15].ff_inst/Q", "phy_name":"CNT01.SLICE_0/Q0" }, "path_end": { "type":"pin", "log_name":"CNT01/Couti[15].ff_inst/DF", "phy_name":"CNT01.SLICE_0/DI0" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"CNT01/Couti[15].ff_inst/CLK", "phy_name":"CNT01.SLICE_0/CLK" }, "pin1": { "log_name":"CNT01/Couti[15].ff_inst/Q", "phy_name":"CNT01.SLICE_0/Q0" }, "arrive":3.031, "delay":0.173 }, { "type":"net_delay", "net": { "log_name":"CNT01/CNT1_15", "phy_name":"CNT1[15]" }, "arrive":3.103, "delay":0.072 }, { "type":"site_delay", "pin0": { "log_name":"CNT01/un3_couti_s_15_0/A0", "phy_name":"CNT01.SLICE_0/A0" }, "pin1": { "log_name":"CNT01/un3_couti_s_15_0/S0", "phy_name":"CNT01.SLICE_0/F0" }, "arrive":3.219, "delay":0.116 }, { "type":"net_delay", "net": { "log_name":"CNT01/un3_couti[15]", "phy_name":"CNT01.un3_couti[15]" }, "arrive":3.219, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":3.219, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- --------------- ------------- ----- --------------------- ------ CNT01/Couti[15].ff_inst/CLK->CNT01/Couti[15].ff_inst/Q SLICE_R14C14A REG_DEL 0.173 3.031 2 CNT01/CNT1_15 NET DELAY 0.072 3.103 2 CNT01/un3_couti_s_15_0/A0->CNT01/un3_couti_s_15_0/S0 SLICE_R14C14A CTOF_DEL 0.116 3.219 1 CNT01/un3_couti[15] NET DELAY 0.000 3.219 1 CNT01/Couti[15].ff_inst/DF 0.000 3.219 1 Destination Clock Path { "path_begin": { "type":"port", "log_name":"CLK1", "phy_name":"CLK1" }, "path_end": { "type":"pin", "log_name":"CNT01/Couti[15].ff_inst/CLK", "phy_name":"CNT01.SLICE_0/CLK" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":0.000, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"CLK1", "phy_name":"CLK1" }, "arrive":0.000, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"CLK1_pad.bb_inst/B", "phy_name":"CLK1_pad.bb_inst/IOPAD" }, "pin1": { "log_name":"CLK1_pad.bb_inst/O", "phy_name":"CLK1_pad.bb_inst/PADDI" }, "arrive":1.000, "delay":1.000 }, { "type":"net_delay", "net": { "log_name":"RST001/CLK1_c", "phy_name":"CLK1_c" }, "arrive":2.858, "delay":1.858 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":2.858, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- --------------- ------------- ----- --------------------- ------ CONSTRAINT 0.000 0.000 1 CLK1 Top CLOCK LATENCY 0.000 0.000 1 CLK1 NET DELAY 0.000 0.000 1 CLK1_pad.bb_inst/B->CLK1_pad.bb_inst/O SEIO33_CORE_P24 PADI_DEL 1.000 1.000 11 RST001/CLK1_c NET DELAY 1.858 2.858 11 CNT01/Couti[15].ff_inst/CLK 0.000 2.858 1 Uncertainty 0.000 2.858 Hold time 0.114 2.972 ---------------------------------------- --------------- ------------- ----- --------------------- ------ Required Time -2.972 Arrival Time 3.219 ---------------------------------------- --------------- ------------- ----- --------------------- ------ Path Slack (Passed) 0.247 ++++ Path 9 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : CNT02/Couti_reg[9].ff_inst/Q (SLICE_R30C82B) Path End : CNT02/Couti_reg[9].ff_inst/DF (SLICE_R30C82B) Source Clock : clk2 (R) Destination Clock: clk2 (R) Logic Level : 2 Delay Ratio : 19.9% (route), 80.1% (logic) Clock Skew : 0.000 ns Hold Constraint : 0.000 ns Path Slack : 0.247 ns (Passed) Source Clock Path { "path_begin": { "type":"port", "log_name":"clk2", "phy_name":"clk2" }, "path_end": { "type":"pin", "log_name":"CNT02/Couti_reg[9].ff_inst/CLK", "phy_name":"CNT02.SLICE_12/CLK" }, "path_sections":[ { "type":"net_delay", "net": { "log_name":"clk2", "phy_name":"clk2" }, "arrive":0.000, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"clk2_pad.bb_inst/B", "phy_name":"clk2_pad.bb_inst/IOPAD" }, "pin1": { "log_name":"clk2_pad.bb_inst/O", "phy_name":"clk2_pad.bb_inst/PADDI" }, "arrive":1.000, "delay":1.000 }, { "type":"net_delay", "net": { "log_name":"RST002/clk2_c", "phy_name":"clk2_c" }, "arrive":2.774, "delay":1.774 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":2.774, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- --------------- ------------- ----- --------------------- ------ clk2 Top CLOCK LATENCY 0.000 0.000 1 clk2 NET DELAY 0.000 0.000 1 clk2_pad.bb_inst/B->clk2_pad.bb_inst/O SEIO33_CORE_P22 PADI_DEL 1.000 1.000 11 RST002/clk2_c NET DELAY 1.774 2.774 11 {CNT02/Couti_reg[9].ff_inst/CLK CNT02/Couti_reg[10].ff_inst/CLK} 0.000 2.774 1 Data Path { "path_begin": { "type":"pin", "log_name":"CNT02/Couti_reg[9].ff_inst/Q", "phy_name":"CNT02.SLICE_12/Q0" }, "path_end": { "type":"pin", "log_name":"CNT02/Couti_reg[9].ff_inst/DF", "phy_name":"CNT02.SLICE_12/DI0" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"CNT02/Couti_reg[9].ff_inst/CLK", "phy_name":"CNT02.SLICE_12/CLK" }, "pin1": { "log_name":"CNT02/Couti_reg[9].ff_inst/Q", "phy_name":"CNT02.SLICE_12/Q0" }, "arrive":2.947, "delay":0.173 }, { "type":"net_delay", "net": { "log_name":"CNT02/Couti[9]", "phy_name":"CNT02.Couti[9]" }, "arrive":3.019, "delay":0.072 }, { "type":"site_delay", "pin0": { "log_name":"CNT02/un3_couti_cry_9_0/A0", "phy_name":"CNT02.SLICE_12/A0" }, "pin1": { "log_name":"CNT02/un3_couti_cry_9_0/S0", "phy_name":"CNT02.SLICE_12/F0" }, "arrive":3.135, "delay":0.116 }, { "type":"net_delay", "net": { "log_name":"CNT02/un3_couti[9]", "phy_name":"CNT02.un3_couti[9]" }, "arrive":3.135, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":3.135, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- --------------- ------------- ----- --------------------- ------ CNT02/Couti_reg[9].ff_inst/CLK->CNT02/Couti_reg[9].ff_inst/Q SLICE_R30C82B REG_DEL 0.173 2.947 1 CNT02/Couti[9] NET DELAY 0.072 3.019 1 CNT02/un3_couti_cry_9_0/A0->CNT02/un3_couti_cry_9_0/S0 SLICE_R30C82B CTOF_DEL 0.116 3.135 1 CNT02/un3_couti[9] NET DELAY 0.000 3.135 1 CNT02/Couti_reg[9].ff_inst/DF 0.000 3.135 1 Destination Clock Path { "path_begin": { "type":"port", "log_name":"clk2", "phy_name":"clk2" }, "path_end": { "type":"pin", "log_name":"CNT02/Couti_reg[9].ff_inst/CLK", "phy_name":"CNT02.SLICE_12/CLK" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":0.000, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"clk2", "phy_name":"clk2" }, "arrive":0.000, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"clk2_pad.bb_inst/B", "phy_name":"clk2_pad.bb_inst/IOPAD" }, "pin1": { "log_name":"clk2_pad.bb_inst/O", "phy_name":"clk2_pad.bb_inst/PADDI" }, "arrive":1.000, "delay":1.000 }, { "type":"net_delay", "net": { "log_name":"RST002/clk2_c", "phy_name":"clk2_c" }, "arrive":2.774, "delay":1.774 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":2.774, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- --------------- ------------- ----- --------------------- ------ CONSTRAINT 0.000 0.000 1 clk2 Top CLOCK LATENCY 0.000 0.000 1 clk2 NET DELAY 0.000 0.000 1 clk2_pad.bb_inst/B->clk2_pad.bb_inst/O SEIO33_CORE_P22 PADI_DEL 1.000 1.000 11 RST002/clk2_c NET DELAY 1.774 2.774 11 {CNT02/Couti_reg[9].ff_inst/CLK CNT02/Couti_reg[10].ff_inst/CLK} 0.000 2.774 1 Uncertainty 0.000 2.774 Hold time 0.114 2.888 ---------------------------------------- --------------- ------------- ----- --------------------- ------ Required Time -2.888 Arrival Time 3.135 ---------------------------------------- --------------- ------------- ----- --------------------- ------ Path Slack (Passed) 0.247 ++++ Path 10 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Path Begin : CNT02/Couti[15].ff_inst/Q (SLICE_R30C83A) Path End : CNT02/Couti[15].ff_inst/DF (SLICE_R30C83A) Source Clock : clk2 (R) Destination Clock: clk2 (R) Logic Level : 2 Delay Ratio : 19.9% (route), 80.1% (logic) Clock Skew : 0.000 ns Hold Constraint : 0.000 ns Path Slack : 0.247 ns (Passed) Source Clock Path { "path_begin": { "type":"port", "log_name":"clk2", "phy_name":"clk2" }, "path_end": { "type":"pin", "log_name":"CNT02/Couti[15].ff_inst/CLK", "phy_name":"CNT02.SLICE_9/CLK" }, "path_sections":[ { "type":"net_delay", "net": { "log_name":"clk2", "phy_name":"clk2" }, "arrive":0.000, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"clk2_pad.bb_inst/B", "phy_name":"clk2_pad.bb_inst/IOPAD" }, "pin1": { "log_name":"clk2_pad.bb_inst/O", "phy_name":"clk2_pad.bb_inst/PADDI" }, "arrive":1.000, "delay":1.000 }, { "type":"net_delay", "net": { "log_name":"RST002/clk2_c", "phy_name":"clk2_c" }, "arrive":2.774, "delay":1.774 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":2.774, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- --------------- ------------- ----- --------------------- ------ clk2 Top CLOCK LATENCY 0.000 0.000 1 clk2 NET DELAY 0.000 0.000 1 clk2_pad.bb_inst/B->clk2_pad.bb_inst/O SEIO33_CORE_P22 PADI_DEL 1.000 1.000 11 RST002/clk2_c NET DELAY 1.774 2.774 11 CNT02/Couti[15].ff_inst/CLK 0.000 2.774 1 Data Path { "path_begin": { "type":"pin", "log_name":"CNT02/Couti[15].ff_inst/Q", "phy_name":"CNT02.SLICE_9/Q0" }, "path_end": { "type":"pin", "log_name":"CNT02/Couti[15].ff_inst/DF", "phy_name":"CNT02.SLICE_9/DI0" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"CNT02/Couti[15].ff_inst/CLK", "phy_name":"CNT02.SLICE_9/CLK" }, "pin1": { "log_name":"CNT02/Couti[15].ff_inst/Q", "phy_name":"CNT02.SLICE_9/Q0" }, "arrive":2.947, "delay":0.173 }, { "type":"net_delay", "net": { "log_name":"CNT02/CNT2_15", "phy_name":"CNT2[15]" }, "arrive":3.019, "delay":0.072 }, { "type":"site_delay", "pin0": { "log_name":"CNT02/un3_couti_s_15_0/A0", "phy_name":"CNT02.SLICE_9/A0" }, "pin1": { "log_name":"CNT02/un3_couti_s_15_0/S0", "phy_name":"CNT02.SLICE_9/F0" }, "arrive":3.135, "delay":0.116 }, { "type":"net_delay", "net": { "log_name":"CNT02/un3_couti[15]", "phy_name":"CNT02.un3_couti[15]" }, "arrive":3.135, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":3.135, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- --------------- ------------- ----- --------------------- ------ CNT02/Couti[15].ff_inst/CLK->CNT02/Couti[15].ff_inst/Q SLICE_R30C83A REG_DEL 0.173 2.947 2 CNT02/CNT2_15 NET DELAY 0.072 3.019 2 CNT02/un3_couti_s_15_0/A0->CNT02/un3_couti_s_15_0/S0 SLICE_R30C83A CTOF_DEL 0.116 3.135 1 CNT02/un3_couti[15] NET DELAY 0.000 3.135 1 CNT02/Couti[15].ff_inst/DF 0.000 3.135 1 Destination Clock Path { "path_begin": { "type":"port", "log_name":"clk2", "phy_name":"clk2" }, "path_end": { "type":"pin", "log_name":"CNT02/Couti[15].ff_inst/CLK", "phy_name":"CNT02.SLICE_9/CLK" }, "path_sections":[ { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":0.000, "delay":0.000 }, { "type":"net_delay", "net": { "log_name":"clk2", "phy_name":"clk2" }, "arrive":0.000, "delay":0.000 }, { "type":"site_delay", "pin0": { "log_name":"clk2_pad.bb_inst/B", "phy_name":"clk2_pad.bb_inst/IOPAD" }, "pin1": { "log_name":"clk2_pad.bb_inst/O", "phy_name":"clk2_pad.bb_inst/PADDI" }, "arrive":1.000, "delay":1.000 }, { "type":"net_delay", "net": { "log_name":"RST002/clk2_c", "phy_name":"clk2_c" }, "arrive":2.774, "delay":1.774 }, { "type":"site_delay", "pin0": { "log_name":"", "phy_name":"" }, "pin1": { "log_name":"", "phy_name":"" }, "arrive":2.774, "delay":0.000 } ] } Name Cell/Site Name Delay Name Incr Arrival/Required Time Fanout ---------------------------------------- --------------- ------------- ----- --------------------- ------ CONSTRAINT 0.000 0.000 1 clk2 Top CLOCK LATENCY 0.000 0.000 1 clk2 NET DELAY 0.000 0.000 1 clk2_pad.bb_inst/B->clk2_pad.bb_inst/O SEIO33_CORE_P22 PADI_DEL 1.000 1.000 11 RST002/clk2_c NET DELAY 1.774 2.774 11 CNT02/Couti[15].ff_inst/CLK 0.000 2.774 1 Uncertainty 0.000 2.774 Hold time 0.114 2.888 ---------------------------------------- --------------- ------------- ----- --------------------- ------ Required Time -2.888 Arrival Time 3.135 ---------------------------------------- --------------- ------------- ----- --------------------- ------ Path Slack (Passed) 0.247 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ End of Detailed Report for timing paths +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ ##########################################################

















































    Contents