Copyright (c) 2002-2022 Lattice Semiconductor Corporation,  All rights reserved.

Fri Dec  1 10:23:40 2023

Command Line: par -w -n 1 -t 1 -s 1 -cores 1 -pack 0 -exp parPathBased=ON \
	LAB04_impl1_map.udb LAB04_impl1.udb 


Cost Table Summary
Level/       Number       Worst        Timing       Worst        Timing       Run          Run
Cost [udb]   Unrouted     Slack        Score        Slack(hold)  Score(hold)  Time         Status
----------   --------     -----        ------       -----------  -----------  ----         ------
5_1   *      0            1.361        0            0.162        0            18           Completed
* : Design saved.

Total (real) run time for 1-seed: 18 secs 

par done!

Lattice Place and Route Report for Design "LAB04_impl1_map.udb"
Fri Dec  1 10:23:40 2023


Best Par Run
PAR: Place And Route Radiant Software (64-bit) 2023.1.1.200.1.
Command Line: par -w -t 1 -cores 1 -pack 0 -exp parPathBased=ON \
	LAB04_impl1_map.udb LAB04_impl1_par.dir/5_1.udb 

Loading LAB04_impl1_map.udb ...
Loading device for application GENERIC from file 'jd5d80.nph' in environment: C:/lscc/radiant/2023.1/ispfpga.
Package Status:                     Final          Version 16.
Performance Hardware Data Status:   Final          Version 3.9.



Design:  Top
Family:  LFCPNX
Device:  LFCPNX-100
Package: LFG672
Performance Grade:   9_High-Performance_1.0V

Device SLICE utilization summary after final SLICE packing:
   SLICE             22/39936        <1% used

Number of Signals: 92
Number of Connections: 137

Device utilization summary:

   GSR                   1/1           100% used
   SIOLOGIC              2/300           1% used
   SEIO33                6/299           2% used
                         6/167           3% bonded
   SLICE                22/39936        <1% used
     LUT                40/79872        <1% used
     REG                36/79872        <1% used


Pin Constraint Summary:
   3 out of 6 pins locked (50% locked).
.
Starting Placer Phase 0 (HIER). CPU time: 0 secs , REAL time: 6 secs 
.........
Finished Placer Phase 0 (HIER). CPU time: 0 secs , REAL time: 6 secs 

Starting Placer Phase 1. CPU time: 0 secs , REAL time: 6 secs 
..  ..
....................

Placer score = 42243.
Finished Placer Phase 1. CPU time: 1 secs , REAL time: 11 secs 

Starting Placer Phase 2.
.

Placer score =  42172
Finished Placer Phase 2.  CPU time: 1 secs , REAL time: 11 secs 

After final PLC packing legalization, all 0 SLICEs that were not satisfying 1 CLK/CE/LSR per HALF-PLC restriction are all placed into compatible PLCs.


Clock Report

Global Clock Resources:
  CLK_PIN    : 2 out of 26 (7%)
  PLL        : 0 out of 4 (0%)
  PCS        : 0 out of 2 (0%)
  DCS        : 0 out of 2 (0%)
  DCC        : 0 out of 62 (0%)
  ECLKDIV    : 0 out of 12 (0%)
  PCLKDIV    : 0 out of 2 (0%)
  OSC        : 0 out of 1 (0%)

Global Clocks:
  PRIMARY "CLK1_c" from comp "CLK1" on CLK_PIN site "P24 (PL42A)", clk load = 11, ce load = 0, sr load = 0
  PRIMARY "clk2_c" from comp "clk2" on CLK_PIN site "P22 (PL44A)", clk load = 11, ce load = 0, sr load = 0

  PRIMARY  : 2 out of 16 (12%)

Edge Clocks:

  No edge clock selected.





I/O Usage Summary (final):
   6 out of 299 (2.0%) SEIO33 sites used.
   6 out of 167 (3.6%) bonded SEIO33 sites used.
   Number of SEIO33 components: 6; differential: 0
   Number of Vref pins used: 0
   0 out of 132 (0.0%) SEIO18 sites used.
   0 out of 132 (0.0%) bonded SEIO18 sites used.
   Number of SEIO18 components: 0; differential: 0
   0 out of 66 (0.0%) DIFFIO18 sites used.
   0 out of 66 (0.0%) bonded DIFFIO18 sites used.
   Number of DIFFIO18 components: 0; differential: 0

I/O Bank Usage Summary:
+----------+---------------+------------+------------+------------+
| I/O Bank | Usage         | Bank Vccio | Bank Vref1 | Bank Vref2 |
+----------+---------------+------------+------------+------------+
| 0        | 0 / 24 (  0%) | -          | -          | -          |
| 1        | 3 / 39 (  7%) | 3.3V       | -          | -          |
| 2        | 0 / 32 (  0%) | -          | -          | -          |
| 3        | 0 / 48 (  0%) | -          | -          | -          |
| 4        | 0 / 48 (  0%) | -          | -          | -          |
| 5        | 0 / 36 (  0%) | -          | -          | -          |
| 6        | 2 / 32 (  6%) | 3.3V       | -          | -          |
| 7        | 1 / 40 (  2%) | 3.3V       | -          | -          |
+----------+---------------+------------+------------+------------+

Total Placer CPU time: 1 secs , REAL time: 11 secs 

Writing design to file LAB04_impl1_par.dir/5_1.udb ...


Start NBR router at 10:23:51 12/01/23

*****************************************************************
Info: NBR allows conflicts(one node used by more than one signal)
      in the earlier iterations. In each iteration, it tries to  
      solve the conflicts while keeping the critical connections 
      routed as short as possible. The routing process is said to
      be completed when no conflicts exist and all connections   
      are routed.                                                
Note: NBR uses a different method to calculate timing slacks. The
      worst slack and total negative slack may not be the same as
      that in timing report. You should always run the timing    
      tool to verify your design.                                
*****************************************************************

Starting routing resource preassignment
Preassignment Summary:
--------------------------------------------------------------------------------
50 connections routed with dedicated routing resources
2 global clock signals routed
72 connections routed (of 137 total) (52.55%)
---------------------------------------------------------
Clock routing summary:
Primary clocks (8 used out of 64 available):
    Signal "CLK1_c" (2, 18, 34, 50)
       Clock   loads: 11    out of    11 routed (100.00%)
    Signal "clk2_c" (4, 20, 36, 52)
       Clock   loads: 11    out of    11 routed (100.00%)
---------------------------------------------------------
--------------------------------------------------------------------------------
Completed routing resource preassignment

Start NBR section for initial routing at 10:23:54 12/01/23
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Routing in Serial Mode ......
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Level 4, iteration 1
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
Estimated worst slack/total negative slack<setup>: 1.361ns/0.000ns; real time: 4 secs 

Info: Initial congestion level at 75.00% usage is 0
Info: Initial congestion area  at 75.00% usage is 0 (0.00%)

Start NBR section for normal routing at 10:23:55 12/01/23
Level 4, iteration 1
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
Estimated worst slack/total negative slack<setup>: 1.361ns/0.000ns; real time: 4 secs 

Start NBR section for setup/hold timing optimization with effort level 3 at 10:23:55 12/01/23

Starting full timing analysis...

Start NBR section for post-routing at 10:23:56 12/01/23

End NBR router with 0 unrouted connection

Starting full timing analysis...


NBR Summary
-----------
  Number of unrouted connections : 0 (0.00%)
  Estimated worst slack<setup> : 1.361ns
  Estimated worst slack<hold > : 0.162ns
  Timing score<setup> : 0
  Timing score<hold > : 0
  Number of connections with timing violations<setup> : 0 (0.00%)
  Number of connections with timing violations<hold > : 0 (0.00%)
-----------


Total CPU time 0 secs 
Total REAL time: 6 secs 
Completely routed.
End of route.  137 routed (100.00%); 0 unrouted.

Writing design to file LAB04_impl1_par.dir/5_1.udb ...


All signals are completely routed.


PAR_SUMMARY::Run status = Completed
PAR_SUMMARY::Number of unrouted conns = 0
PAR_SUMMARY::Worst  slack<setup/<ns>> = 1.361
PAR_SUMMARY::Timing score<setup/<ns>> = 0.000
PAR_SUMMARY::Worst  slack<hold /<ns>> = 0.162
PAR_SUMMARY::Timing score<hold /<ns>> = 0.000
PAR_SUMMARY::Number of errors = 0

Total CPU  Time: 2 secs 
Total REAL Time: 18 secs 
Peak Memory Usage: 677.33 MB


par done!

Note: user must run 'timing' for timing closure signoff.

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Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2023 Lattice Semiconductor Corporation,  All rights reserved.





















































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