Copyright (c) 2002-2022 Lattice Semiconductor Corporation, All rights reserved. Thu Nov 30 09:29:33 2023 Command Line: par -w -n 1 -t 1 -s 1 -cores 1 -pack 0 -exp parPathBased=ON \ LAB04_Async_rst_map.udb LAB04_Async_rst.udb Cost Table Summary Level/ Number Worst Timing Worst Timing Run Run Cost [udb] Unrouted Slack Score Slack(hold) Score(hold) Time Status ---------- -------- ----- ------ ----------- ----------- ---- ------ 5_1 * 0 3.085 0 0.162 0 24 Completed * : Design saved. Total (real) run time for 1-seed: 24 secs par done! Lattice Place and Route Report for Design "LAB04_Async_rst_map.udb" Thu Nov 30 09:29:33 2023 Best Par Run PAR: Place And Route Radiant Software (64-bit) 2023.1.1.200.1. Command Line: par -w -t 1 -cores 1 -pack 0 -exp parPathBased=ON \ LAB04_Async_rst_map.udb LAB04_Async_rst_par.dir/5_1.udb Loading LAB04_Async_rst_map.udb ... Loading device for application GENERIC from file 'jd5d80.nph' in environment: C:/lscc/radiant/2023.1/ispfpga. Package Status: Final Version 16. Performance Hardware Data Status: Final Version 3.9. Design: Top Family: LFCPNX Device: LFCPNX-100 Package: LFG672 Performance Grade: 9_High-Performance_1.0V Device SLICE utilization summary after final SLICE packing: SLICE 781/39936 1% used Number of Signals: 2557 Number of Connections: 6902 Device utilization summary: GSR 1/1 100% used VHI 1/1 100% used SIOLOGIC 3/300 1% used EBR 2/208 1% used SEIO18A 1/132 1% used 1/132 0% bonded SEIO33 9/299 3% used 9/167 5% bonded OSC 1/1 100% used CONFIG_JTAG 1/1 100% used SLICE 781/39936 2% used LUT 1476/79872 2% used REG 1008/79872 1% used Pin Constraint Summary: 6 out of 10 pins locked (60% locked). Starting Placer Phase 0 (HIER). CPU time: 4 secs , REAL time: 6 secs .......... Finished Placer Phase 0 (HIER). CPU time: 4 secs , REAL time: 6 secs Starting Placer Phase 1. CPU time: 4 secs , REAL time: 6 secs .. .. ................ Placer score = 780121. Finished Placer Phase 1. CPU time: 7 secs , REAL time: 12 secs Starting Placer Phase 2. . Placer score = 775656 Finished Placer Phase 2. CPU time: 7 secs , REAL time: 12 secs After final PLC packing legalization, all 0 SLICEs that were not satisfying 1 CLK/CE/LSR per HALF-PLC restriction are all placed into compatible PLCs. Clock Report Global Clock Resources: CLK_PIN : 0 out of 26 (0%) PLL : 0 out of 4 (0%) PCS : 0 out of 2 (0%) DCS : 0 out of 2 (0%) DCC : 0 out of 62 (0%) ECLKDIV : 0 out of 12 (0%) PCLKDIV : 0 out of 2 (0%) OSC : 1 out of 1 (100%) Global Clocks: PRIMARY "clk150" from HFCLKOUT on comp "OSCA001.OSCA_inst" on site "OSC_CORE_R1C137", clk load = 343, ce load = 0, sr load = 0 PRIMARY "jtck" from JTCK on comp "jtaghub_inst.jtagg_u" on site "TCONFIG_JTAG_CORE145", clk load = 291, ce load = 0, sr load = 0 PRIMARY : 2 out of 16 (12%) Edge Clocks: No edge clock selected. I/O Usage Summary (final): 9 out of 299 (3.0%) SEIO33 sites used. 9 out of 167 (5.4%) bonded SEIO33 sites used. Number of SEIO33 components: 9; differential: 0 Number of Vref pins used: 0 1 out of 132 (0.8%) SEIO18 sites used. 1 out of 132 (0.8%) bonded SEIO18 sites used. Number of SEIO18 components: 1; differential: 0 0 out of 66 (0.0%) DIFFIO18 sites used. 0 out of 66 (0.0%) bonded DIFFIO18 sites used. Number of DIFFIO18 components: 0; differential: 0 I/O Bank Usage Summary: +----------+---------------+------------+------------+------------+ | I/O Bank | Usage | Bank Vccio | Bank Vref1 | Bank Vref2 | +----------+---------------+------------+------------+------------+ | 0 | 0 / 24 ( 0%) | - | - | - | | 1 | 9 / 39 ( 23%) | 3.3V | - | - | | 2 | 0 / 32 ( 0%) | - | - | - | | 3 | 0 / 48 ( 0%) | - | - | - | | 4 | 0 / 48 ( 0%) | - | - | - | | 5 | 1 / 36 ( 2%) | 1.8V | - | - | | 6 | 0 / 32 ( 0%) | - | - | - | | 7 | 0 / 40 ( 0%) | - | - | - | +----------+---------------+------------+------------+------------+ Total Placer CPU time: 7 secs , REAL time: 12 secs Writing design to file LAB04_Async_rst_par.dir/5_1.udb ... Start NBR router at 09:29:45 11/30/23 ***************************************************************** Info: NBR allows conflicts(one node used by more than one signal) in the earlier iterations. In each iteration, it tries to solve the conflicts while keeping the critical connections routed as short as possible. The routing process is said to be completed when no conflicts exist and all connections are routed. Note: NBR uses a different method to calculate timing slacks. The worst slack and total negative slack may not be the same as that in timing report. You should always run the timing tool to verify your design. ***************************************************************** Starting routing resource preassignment Preassignment Summary: -------------------------------------------------------------------------------- 619 connections routed with dedicated routing resources 2 global clock signals routed 1293 connections routed (of 6902 total) (18.73%) --------------------------------------------------------- Clock routing summary: Primary clocks (8 used out of 64 available): Signal "jtck" (4, 20, 36, 52) Clock loads: 291 out of 291 routed (100.00%) Signal "clk150" (3, 19, 35, 51) Clock loads: 343 out of 343 routed (100.00%) --------------------------------------------------------- -------------------------------------------------------------------------------- Completed routing resource preassignment Start NBR section for initial routing at 09:29:49 11/30/23 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Routing in Serial Mode ...... +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Level 4, iteration 1 1681(0.04%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack<setup>: 3.129ns/0.000ns; real time: 5 secs Info: Initial congestion level at 75.00% usage is 0 Info: Initial congestion area at 75.00% usage is 0 (0.00%) Start NBR section for normal routing at 09:29:50 11/30/23 Level 4, iteration 1 1385(0.03%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack<setup>: 3.113ns/0.000ns; real time: 6 secs Level 4, iteration 2 700(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack<setup>: 3.085ns/0.000ns; real time: 6 secs Level 4, iteration 3 421(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack<setup>: 3.085ns/0.000ns; real time: 7 secs Level 4, iteration 4 283(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack<setup>: 3.085ns/0.000ns; real time: 7 secs Level 4, iteration 5 172(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack<setup>: 3.085ns/0.000ns; real time: 7 secs Level 4, iteration 6 135(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack<setup>: 3.085ns/0.000ns; real time: 7 secs Level 4, iteration 7 103(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack<setup>: 3.085ns/0.000ns; real time: 7 secs Level 4, iteration 8 54(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack<setup>: 3.085ns/0.000ns; real time: 7 secs Level 4, iteration 9 34(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack<setup>: 3.085ns/0.000ns; real time: 7 secs Level 4, iteration 10 21(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack<setup>: 3.085ns/0.000ns; real time: 8 secs Level 4, iteration 11 17(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack<setup>: 3.085ns/0.000ns; real time: 8 secs Level 4, iteration 12 9(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack<setup>: 3.085ns/0.000ns; real time: 8 secs Level 4, iteration 13 8(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack<setup>: 3.085ns/0.000ns; real time: 8 secs Level 4, iteration 14 7(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack<setup>: 3.085ns/0.000ns; real time: 8 secs Level 4, iteration 15 6(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack<setup>: 3.085ns/0.000ns; real time: 8 secs Level 4, iteration 16 2(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack<setup>: 3.085ns/0.000ns; real time: 8 secs Level 4, iteration 17 1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack<setup>: 3.085ns/0.000ns; real time: 8 secs Level 4, iteration 18 1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack<setup>: 3.085ns/0.000ns; real time: 8 secs Level 4, iteration 19 1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack<setup>: 3.085ns/0.000ns; real time: 8 secs Level 4, iteration 20 1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack<setup>: 3.085ns/0.000ns; real time: 8 secs Level 4, iteration 21 2(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack<setup>: 3.085ns/0.000ns; real time: 8 secs Level 4, iteration 22 0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack<setup>: 3.085ns/0.000ns; real time: 8 secs Start NBR section for setup/hold timing optimization with effort level 3 at 09:29:53 11/30/23 Starting full timing analysis... Start NBR section for post-routing at 09:29:55 11/30/23 End NBR router with 0 unrouted connection Starting full timing analysis... NBR Summary ----------- Number of unrouted connections : 0 (0.00%) Estimated worst slack<setup> : 3.085ns Estimated worst slack<hold > : 0.162ns Timing score<setup> : 0 Timing score<hold > : 0 Number of connections with timing violations<setup> : 0 (0.00%) Number of connections with timing violations<hold > : 0 (0.00%) ----------- Total CPU time 6 secs Total REAL time: 11 secs Completely routed. End of route. 6902 routed (100.00%); 0 unrouted. Writing design to file LAB04_Async_rst_par.dir/5_1.udb ... All signals are completely routed. PAR_SUMMARY::Run status = Completed PAR_SUMMARY::Number of unrouted conns = 0 PAR_SUMMARY::Worst slack<setup/<ns>> = 3.085 PAR_SUMMARY::Timing score<setup/<ns>> = 0.000 PAR_SUMMARY::Worst slack<hold /<ns>> = 0.162 PAR_SUMMARY::Timing score<hold /<ns>> = 0.000 PAR_SUMMARY::Number of errors = 0 Total CPU Time: 15 secs Total REAL Time: 24 secs Peak Memory Usage: 703.11 MB par done! Note: user must run 'timing' for timing closure signoff. Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2023 Lattice Semiconductor Corporation, All rights reserved.