Project Settings
Project Name proj_1 Device Name Async_rst: Lattice LFCPNX : LFCPNX_100
Implementation Name Async_rst Top Module Top
Pipelining 1 Retiming 0
Resource Sharing 1 Fanout Guide 1000
Disable I/O Insertion 0 Disable Sequential Optimizations 0
Clock Conversion 0 FSM Compiler 1

Run Status
Job Name Status CPU Time Real Time Memory Date/Time
(compiler)Complete 159 30 0 - 00m:10s - 2023-11-30
9:29 AM
(premap)Complete 5 132 0 0m:00s 0m:02s 207MB 2023-11-30
9:29 AM
(fpga_mapper)Complete 12 5 0 0m:02s 0m:08s 224MB 2023-11-30
9:29 AM
Multi-srs Generator Complete00m:01s2023-11-30
9:29 AM

Area Summary
Register bits 962 I/O cells 6
Block RAMs (v_ram) 2 DSPs (dsp_used) 0
LUTs (total_luts) 954

Timing Summary
Clock NameReq FreqEst FreqSlack
Top|clk1501.0 MHz257.8 MHz996.121
Top|jtck_inferred_clock1.0 MHz165.2 MHz993.947
rvltck30.0 MHzNANA
System1.0 MHz305.5 MHz996.727

Optimizations Summary
Combined Clock Conversion 2 / 0